TCM4400E Datasheet, PDF (50/64 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
PRINCIPLES OF OPERATION
baseband control register (see Table 15)
The values in the baseband control register bit positions determine whether the data is shifted left or right. Note
that the microcontroller unit (MCU) clocking scheme determines on which edge of the clock that data is received
or transmitted using the serial interface.
Table 15. Baseband Control Register
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{BCTLREG: BASEBAND CONTROL REGISTER}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RESERVD RESERVD RESERVD MCLKBP BCLKMODE BIZBUS BCLKDIR
R=0
R=0
R=0
R /W
R /W
R/W
R/W
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
0
0
0
0
0
0
UDIR
R/W
0
UPHA
R/W
0
UPOL
R/W
0
ADDRESS: 9 R/W
0 1 0 0 1 1/0
<–ACCESS TYPE
<–VALUE AT RESET
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _UDIR:
This bit determines whether the data is shifted in from right (see serial register description) to
left, MSB first (bit value 0), or from left to right, LSB first (bit value 1).
BCLKMODE:When cleared to 0, BLCKX runs in the burst mode; when set to 1, BCLKX is continuous.
MCLKBP: When cleared to 0, MCLK signal passes through the clock slicer; when set to 1, the clock slicer
is bypassed (in this case, the signal at the MCLK terminal must be digital).
MCU clocking schemes
Falling edge without delay: The MCU serial interface transmits data on the falling edge of the UCLK and
receives data on the rising edge of UCLK.
Falling edge with delay: The MCU serial interface transmits data one half-cycle ahead of the falling edge
of the UCLK and receives data on the falling edge of the UCLK.
Rising edge without delay: The MCU serial interface transmits data on the rising edge of the UCLK and
receives data on the falling edge of the UCLK.
Rising edge with delay: The MCU serial interface transmits data one half-cycle ahead of the rising edge
of the UCLK and receives data on the rising edge of UCLK.
BCLKDIR:
Table 16. MCU Clocking Schemes
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _UPOL
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0
0
UPHA
1
0
1
0
MCU CLOCKING SCHEME
Falling edge without delay
Falling edge with delay
Rising edge without delay
Rising edge with delay
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Direction of the BCLKR port ( 0 –> Output, 1–> Input).}
BIZBUS:
When set to 1, BDX, BCLKX, BFSX are in hi-Z when there is nothing to transfer to the DSP;
when cleared to 0, DBX, BCLKX, BFSX are set to V_SS when there is nothing to transfer to the
DSP.
RESRVD: Reserved bits for testing purpose
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