TCM4400E Datasheet, PDF (21/64 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
downlink timing considerations
Figure 2 shows the timing diagram for downlink operation.
Timing control of the baseband downlink path is controlled by bits DLON (downlink on), BCAL (calibration) and
BENA (enable) when BDLON is active (see the topic, timing and interface). BDLON controls the power up of
the baseband downlink path, BCAL controls the start and duration of the autocalibration sequence, and BENA
controls the beginning and the duration of data transmission to the DSP, using the DSP serial interface.
The power-down sequence is controlled with two bits, the first bit (BBDLW of PWDNRG1 register) determines
whether the baseband downlink path can be powered down with external GSM receive window activation
(BDLON); the second bit (BBDLPD of PWDNRG1 register) controls the activation of the baseband downlink
path. See the topic, power-down functional description, for more details about power-down control.
BDLON
BCAL
BENA
DATAOUT
tsu4
tw3
tsu5
tw4
tsu6
Figure 2. Downlink Timing Sequence
th5
th4
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