TI380PCIA Datasheet, PDF (7/40 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS™
SPWS035 – JUNE 1997
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O†
DESCRIPTION
SYSTEM INTERFACE (SIF)‡ (CONTINUED)
SLDS
SOWN
SRESET
Lower data strobe. SLDS is an output during DIO and an input during DMA. SLDS serves as the
active-low lower data strobe.#
1
I/O
H = Not valid data on SADL0 – SADL7 lines
L = Valid data on SADL0 – SADL7 lines
SIF bus owned. SOWN signals the TI380PCIA SIF logic to indicate that the TI380C2x§ has control of
the SIF bus.
126
I
L = TI380PCIA does not have control of the SIF bus.
H = TI380PCIA has control of the SIF bus.
System reset. SRESET is sent to initialize the TI380C2x§. It is set low whenever RST goes low or by
a configuration write to the MISCCTRL register.
17
O
H = No system reset
L = System reset
System read not write. SRNW serves as a control signal to indicate a read or write cycle.
SRNW
128
I / O _{H = Read Cycle}
L = Write Cycle
SRSX
SRS0
SRS1
System register select. These outputs are sent to select the word or byte to be transferred during a
13
system DIO access. The most significant bit is SRSX and the least significant bit is SRS1.
14
O
15
MSB
LSB
Registers selected = SRSX SRS0 SRS1
SUDS
Upper data strobe. SUDS serves as the active-low upper data strobe. SUDS is an output during DIO
and an input during DMA.#
123 I / O
H = Not valid data on SADH0 – SADH7 lines
L = Valid data on SADH0 – SADH7 lines
SXAL
System extended address latch. SXAL provides the enable pulse that externally latches the most
144
I
significant 16 bits of the 32-bit system address during DMA. SXAL is activated by the TI380C2x§ prior
to the first cycle of each block DMA transfer, and thereafter as necessary (whenever an increment of
the DMA address counter causes a carryout of the lower 16 bits).
† _{I = in, O = out}
‡ _{The TI380PCIA SIF pin names correspond to a subset of the system interface pins on a TI380C2x§. See the TI380C2x§ data sheets for more}
information on individual pins. Like-named pins on the TI380PCIA and TI380C2x§ system interfaces are intended to be connected to each
other.
§ _{TI380C3x devices can be used with TI380PCIA in the same way as TI380C2x devices.}
¶ _{Typical bit-ordering for Intel™ and Motorola™ processor buses}
# _{The signal connecting this pin to the TI380C2x§ also should be connected to a 4.7-kΩ pullup resistor.}
|| _{The TI380PCIA BIF pin names correspond to a subset of the local memory bus interface pins on a TI380C2x§. Like-named pins on the two}
devices are intended to be connected to each other. Consult the TI380C2x§ data sheets for more information on individual pins.
NOTE 1: The TI380PCIA allows driver software to set SBCLK output to a steady high state. This signal is driven to a steady high state during
power-down operations.
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