TI380PCIA Datasheet, PDF (6/40 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS™
SPWS035 – JUNE 1997
TERMINAL
NAME
NO.
SBERR
7
SBGR
5
SBRLS
11
SBRQ
129
SCS
12
SDBEN
127
SDTACK
125
Terminal Functions (Continued)
I/O†
DESCRIPTION
SYSTEM INTERFACE (SIF)‡ (CONTINUED)
Bus error. SBERR corresponds to the bus error signal of the 68000 microprocessor. SBERR is driven
O
low during a DMA cycle to indicate to the TI380C2x§ that the cycle must be terminated. See
Section 3.4.5.3 of the TMS380 Second - Generation Token Ring User’s Guide (SPWU005) for more
information.
System-bus grant. SBGR serves as an active-low bus grant, as defined in the standard 68000 interface.
O _{H = System bus not granted}
L = System bus granted
SIF bus release. SBRLS indicates to the TI380C2x§ that a higher-priority device requires the SIF bus.
The value on SBRLS is ignored by the TI380C2x§ when DMA is not performed.
O _{H = The TI380C2x§ can hold onto the system bus.}
L = The TI380C2x§ should release the system bus upon completion of current DMA cycle. If the
DMA transfer is not yet complete, the SIF rearbitrates for the SIF bus.
System-bus request. SBRQ is used to request control of the system bus in preparation for a DMA
transfer. SBRQ is internally synchronized to SBCLK.
I
H = System bus not requested
L = System bus requested
System chip select. SCS activates the system interface of the TI380C2x§ for a DIO read or write.
O _{H = Not selected}
L = Selected
System data-bus enable. SDBEN causes the TI380PCIA to allow its external data buffers to begin
driving data. SDBEN is accepted during both DIO and DMA.
I
H = Keep external data buffers in highĆimpedance state
L = Cause external data buffers to begin driving data
System data-transfer acknowledge. The purpose of SDTACK is to indicate to the bus master that a data
transfer is complete. SDTACK is internally synchronized to SBCLK by the TI380C2x§. During DMA
cycles, it is asserted before the falling edge of SBCLK in state T2 by the TI380PCIA to prevent a wait
I / O state. SDTACK is an input when the TI380C2x§ is selected for DIO, and an output otherwise.#
H = System bus NOT ready
L = Data transfer is complete; system bus is ready.
SHALT
System halt/bus error retry. If SHALT is asserted along with bus error (SBERR), the adapter retries the
3
O last DMA cycle. This is the rerun operation as defined in the 68000 specification. See Section 3.4.5.3
of the TMS380 Second - Generation Token Ring User’s Guide (SPWU005) for more information.
System interrupt request. TI380C2x§ drives SIRQ to signal an interrupt request to the host processor.
SIRQ
6
I _{H = No interrupt request}
L = Interrupt request by TI380C2x§
† _{I = in, O = out}
‡ _{The TI380PCIA SIF pin names correspond to a subset of the system interface pins on a TI380C2x§. See the TI380C2x§ data sheets for more}
information on individual pins. Like-named pins on the TI380PCIA and TI380C2x§ system interfaces are intended to be connected to each
other.
§ _{TI380C3x devices can be used with TI380PCIA in the same way as TI380C2x devices.}
¶ _{Typical bit-ordering for Intel™ and Motorola™ processor buses}
# _{The signal connecting this pin to the TI380C2x§ also should be connected to a 4.7-kΩ pullup resistor.}
|| _{The TI380PCIA BIF pin names correspond to a subset of the local memory bus interface pins on a TI380C2x§. Like-named pins on the two}
devices are intended to be connected to each other. Consult the TI380C2x§ data sheets for more information on individual pins.
NOTE 1: The TI380PCIA allows driver software to set SBCLK output to a steady high state. This signal is driven to a steady high state during
power-down operations.
6
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443