TI380PCIA Datasheet, PDF (26/40 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS™
SPWS035 – JUNE 1997
miscellaneous control register (MISCCTRL) — configuration space DWORD address (0x40)
Figure 13 shows the layout of the miscellaneous control register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA Channels
INT
Speed and
Topology
Connector
Reserved
Sleep
Expansion ROM
Address Mode
Reserved
SBCLK Divide
Ratio
Reserved
Address Parity
Error
Target-Reported
Parity Error
Retry Count
Expired
Software-Reset
Figure 13. Miscellaneous Control Register Layout
The MISCCTRL is a collection of LAN subsystem control functions. The value of the bit fields in this register
after reset are as indicated.
Bits 00 – 03: DMA channels. DMA channel has no meaning in a PCI context. These four bits also appear in the
TI2000 configuration register where they select between bus master DMA operation and pseudo-DMA
operation as defined by the TI2000 software specification. When this field has the value of 0xF, a TI2000 driver
operates in pseudo-DMA mode. For all other values, TI2000 drivers operate in bus master DMA mode.
Bits 04 – 07: INT. The four INT bits indicate the interrupt level. At reset, these bits are set to 0x0. They are
read-only bits and they echo the least significant four bits of the interrupt line register.
Bits 08 – 09: Speed and topology. These bits are echoed in bits 8 – 9 of the TI2000 configuration register (see
Table 6). At reset, these bits are set to 0x1 (Token Ring 16 Mbps).
Table 6. Speed and Topology Bits
SPEED BIT 9
0
1
0
1
TOPOLOGY BIT 8
0
0
1
1
DESCRIPTION
Full-duplex Ethernet^®
Ethernet
Token Ring 16 Mbps
Token Ring 4 Mbps
Ethernet is a registered trademark of Xerox Corporation.
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