TI380PCIA Datasheet, PDF (14/40 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS™
SPWS035 – JUNE 1997
ROM interface (ROMIF) (continued)
its internal page register. The TI2000 software standard requires that writes to the ROM location increment to
the next 16K page and that the ROM pages be cycled through only once until the next reset. Note that ROMCS
does not go low when the host attempts to write to the EPROM.
When RST is driven high, the value on ROMA[07:00] is latched into the board configuration register in the
TI380PCIA configuration space (DWORD address 0x44). The value on ROMA[07:00] can be provided by pullup
and pulldown resistors that do not affect operation after reset. This feature allows designers to support jumpers
or board-stuffing options sensed by software that reads the board configuration register. If pullup and pulldown
registers are not used, the contents of the board configuration register are undefined after reset.
When the host computer initiates a 32-bit read to the ROMIF, the TI380PCIA fetches four bytes from the ROM
and presents the resulting 32-bit DWORD to the PCI bus. The fetches from the ROM start with the least
significant byte, byte 0, followed by bytes 1, 2, and 3. The data is presented to the PCI data bus as shown in
Figure 3.
AD31
AD24 AD23
TI380PCIA PCI DATA BUS PINS
AD16 AD15
AD08 AD07
AD00
BYTE 3
BYTE 2
BYTE 1
BYTE 0
ROMA00
ROMA00 ROMA07
ROMA00 ROMA07
ROMA00 ROMA07
TI380PCIA ROM DATA BUS PINS
ROMA00
Figure 3. PCI Bus Data
The ROMIF has been designed for operation with EPROM devices with 100-ns access times.
serial EEPROM interface (EIF)
The TI380PCIA includes an interface for an optional I²C serial EEPROM. The EEPROM contains the following:
D Bytes 0x0 – 0x7 contain eight bytes of PCI configuration information that are automatically loaded into the
appropriate PCI configuration register by the TI380PCIA at power-on.
D Byte 0x8 is a checksum calculated on bytes 0 – 7. This checksum byte is automatically read at power-on
by the TI380PCIA. If the checksum read from byte 8 does not agree with the checksum that the TI380PCIA
calculated from bytes 0 – 7, then the TI380PCIA sets the ECRCERR and NEP bits in the EEPROM
read/write register in TI380PCIA configuration space.
D Bytes 0x09 – 0x10 contain the six bytes of the BIA and two bytes of the BIA checksum. The TI380PCIA reads
these bytes and stores them in an internal register, the contents of which are presented to the TI380C2x^†
local memory bus when the TI380PCIA detects an access to the BIA. In this way, the TI380PCIA emulates
the presence of a BIA ROM on the TI380C2x^† local memory bus. The TI380PCIA does not verify the BIA
checksum.
D Byte 0x11 is reserved for use by TI2000 drivers. This byte is not read automatically by the TI380PCIA, but
it is read by TI2000 drivers that load bit 0 from this byte into the TI380PCIA MISCCTRL register bit 8 and
load bit 1 from this byte into TI380PCIA MISCCTRL register bit 9. This byte allows the TI2000 driver to read
the network speed and topology from nonvolatile memory before attempting to access the network.
D Bytes 0x12 – 0x20 are reserved for future use by the TI380PCIA.
D Bytes 0x21 – 0xFF are available for user-defined variable storage.
† _{TI380C3x devices can be used with TI380PCIA in the same way as TI380C2x devices.}
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