TI380PCIA Datasheet, PDF (25/40 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS™
SPWS035 – JUNE 1997
interrupt line—configuration space DWORD address (0x3C)
TI380PCIA uses a PCI bus interrupt so this register is implemented as an 8-bit read / write register. The value
after reset is 0x00. The least significant four bits are passed to the MISCCTRL register and the TI2000
configuration register.
interrupt pin—configuration space DWORD address (0x3C)
This is hardwired to 0x01 to indicate that INTA is used as the interrupt pin.
minimum grant (Min_Gnt)—configuration space DWORD address (0x3C)
This register is loaded with a value from the EEPROM. If no EEPROM is present, the register is loaded with
0x01.
maximum latency (Max_Lat)—configuration space DWORD address (0x3C)
The TI380C2x^† uses a buffer that is larger than 1K byte to store network data; therefore, at the maximum
network data rate of 16 Mbps, the TI380C2x^† can be serviced at intervals greater than 64 µs. This register is
loaded with a value from the EEPROM. If no EEPROM is present, the register is loaded with 0x00.
subsystem-specific registers
The TI380PCIA contains the following registers in addition to the PCI-prescribed registers:
D Miscellaneous control register
D Board configuration register
D EEPROM read / write register
D TI380PCIA interface control register
D TI2000 configuration register
These registers are described in this section.
† _{TI380C3x devices can be used with TI380PCIA in the same way as TI380C2x devices.}
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