TI380PCIA Datasheet, PDF (10/40 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS™
SPWS035 – JUNE 1997
TERMINAL
NAME
NO.
FRAME
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Terminal Functions (Continued)
I/O†
DESCRIPTION
PCI INTERFACE (CONTINUED)
Cycle frame. FRAME is driven by the current master to indicate the beginning and duration of an access.
I /O It is asserted to indicate that a bus transaction is beginning. While FRAME is asserted, data transfers
continue. When FRAME is deasserted, the transaction is in the final data phase.
GNT
IDSEL
INTA
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I ^{Grant. GNT indicates to the TI380PCIA that access to the PCI bus has been granted. This is a}
point-to-point signal.
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I
Initialization device select. IDSEL is used as a chip-select during configuration read and write
transactions.
20
O
Interrupt A. INTA is used to request an interrupt. The assertion and deassertion of INTA is asynchronous
to PCLK.
IRDY
Initiator ready. IRDY indicates that the bus master can complete the current data phase of the
transaction. If a data phase is completed on any clock, both IRDY and TRDY are sampled and asserted.
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I /O During a write, IRDY indicates that valid data is present on AD31 – AD00. During a read, it indicates that
the master is prepared to accept data. Wait cycles are inserted until both IRDY and TRDY are asserted
together.
Parity. PAR carries even parity across AD31 – AD00 and C / BE3 – C / BE0. It is driven by the master for
PAR
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I/O
address and write data phases; it is driven by the target for read data phases. PAR is valid one clock
after the address phase. For data phases, PAR is valid one clock after either IRDY (for a write) or TRDY
(for a read) is asserted.
PCLK
Clock. PCLK provides timing for all transactions on the PCI bus. All other PCI signals, except RST and
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I INTA, are sampled on the rising edge of PCLK. PCLK is used to generate the SBCLK signal that goes
to the TI380C2x§.
PERR
Parity error. PERR is for the reporting of data parity errors during all transactions. It is driven active by
the agent receiving data two clocks following the data when a data parity error is detected. The minimum
duration of PERR is one clock for each data phase that a data parity error is detected.
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I/O
There are no special conditions when a PERR can be lost or when reporting of an error can be delayed.
An agent cannot report a PERR until it has claimed the access by asserting DEVSEL and completing
a data phase.
REQ
Request. REQ indicates to the arbiter that TI380PCIA desires use of the bus. REQ is a point-to-point
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O _signal.
Reset. RST is used to hard-reset the LAN subsystem, including TI380C2x§ and the TI380PCIA.
RST
21
I _{To prevent ADxx, C / BEx, and PAR signals from floating during reset, the central device can drive these}
lines during reset (bus-parking) but only to a logic-low level; these cannot be driven high.
SERR
System error. SERR, when enabled, reports address parity errors or any other system error where the
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I / O result is catastrophic. The assertion of SERR is synchronous to the clock and meets the setup and hold
times of all PCI signals.
STOP
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I / O Stop. STOP indicates that the current slave is requesting the master to stop the current transaction.
† _{I = in, O = out}
‡ _{The TI380PCIA SIF pin names correspond to a subset of the system interface pins on a TI380C2x§. See the TI380C2x§ data sheets for more}
information on individual pins. Like-named pins on the TI380PCIA and TI380C2x§ system interfaces are intended to be connected to each
other.
§ _{TI380C3x devices can be used with TI380PCIA in the same way as TI380C2x devices.}
¶ _{Typical bit-ordering for Intel™ and Motorola™ processor buses}
# _{The signal connecting this pin to the TI380C2x§ also should be connected to a 4.7-kΩ pullup resistor.}
|| _{The TI380PCIA BIF pin names correspond to a subset of the local memory bus interface pins on a TI380C2x§. Like-named pins on the two}
devices are intended to be connected to each other. Consult the TI380C2x§ data sheets for more information on individual pins.
NOTE 1: The TI380PCIA allows driver software to set SBCLK output to a steady high state. This signal is driven to a steady high state during
power-down operations.
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