TI380PCIA Datasheet, PDF (17/40 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS™
SPWS035 – JUNE 1997
serial EEPROM interface (EIF) (continued)
The example that follows is an adapter RAM memory dump for a card with BIA = 0001fafe1093.
example:
Address
Data
000000
: 0000 0100 fa00 fe00 1000 9300 0b00 9200
Address
Data
Checksum
01
00
03
01
05
fa
07
fe
09
10
0b
93
0c
0b
0d
92
0001
fafe
+ 1093
_____
(1) 0b92
The EEPROM also can be read and written under software control by PCI configuration register 0x48. A typical
I²C EEPROM that can be used with the TI380PCIA is the 24C02. EEPROMs that provide external address pins
for identification of several devices on the I²C bus should have these address pins pulled down to logic 0.
burned-in address interface (BIF)
The BIF logic is designed to connect directly to the local memory bus of the TI380C2x^†. The BIF serves two
purposes:
D Checks the status cycles on the local memory bus to detect the initialization and completion of DMA
transfers from the TI380C2x^†
D Detects accesses to the BIA ROM from the TI380C2x^†. During a BIA access, the TI380PCIA drives data
onto MADH00 – 07, emulating a BIA programmable read-only memory (PROM). This eliminates the need
for a separate BIA PROM.
in-circuit test NAND tree operation
The terminal function table explains how to use the ICT pins on the TI380PCIA to place the output pins of the
TI380PCIA in a 3-state mode to allow for in-circuit testing of a printed circuit board.
The TI380PCIA also contains a NAND tree that can be used during the in-circuit testing process to verify the
integrity of the solder connections to the TI380PCIA. The NAND tree is activated by latching a control value on
the SADL0–7 pins on the rising edge of the signal applied to the ICT pin.
To activate the NAND tree, complete the following steps:
1. Drive and hold ICT low.
2. Drive and hold the MAX0 input low and drive the MAX2 input high. Drive and hold the SADL0–7 pins as
shown in Figure 6.
3. While holding the values in step 2, pull the ICT input high to latch the values from step 2.
The connections to the TI380PCIA can now be tested with the NAND tree. The NAND tree can be
deactivated by repeating steps 1 through 3 with the data applied to the SADL0–7 pins in step 2 set as shown
in Figure 7.
† _{TI380C3x devices can be used with TI380PCIA in the same way as TI380C2x devices.}
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