TI380PCIA Datasheet, PDF (31/40 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS™
SPWS035 – JUNE 1997
TI2000 configuration register (continued)
Bit 11: INST8. This bit indicates whether the driver can use 16-bit instructions to access adapter registers. It
is hardwired to 0 because PCI-based machines are able to perform 16-bit instructions.
1 = The TI2000 driver must use 8-bit instructions to access the LAN adapter registers.
0 = The TI2000 driver can use 16-bit instructions to access the LAN adapter registers.
Bit 12: DEDMACTL. The Don’t Enable ISA DMA Controller (DEDMACTL) bit indicates whether the TI2000
driver must enable the ISA DMA controller (see Table 12). The ISA DMA controller is not used to control
operations on the PCI bus. To allow the TI2000 software specification to be expanded to comprehend the PCI
bus, this bit is hardwired to a 1 to indicate that a TI2000 driver controlling a PCI-based network interface card
should not enable an ISA DMA controller. (The setting of this bit does not affect DMA on the PCI bus.)
Table 12. ISA DMA Controller Settings
DMA MODE
DMA
DMA
PDMA
DEDMACTL BIT VALUE
1 = Driver must NOT enable ISA DMA controller
0 = Driver must enable ISA DMA controller
x = Driver must NOT enable ISA DMA controller
Bits 13 – 14: Reserved. These bits must be read as 0.
Bit 15: Config. The MSB of the configuration register, when set, indicates the existence of the configuration
register. This bit is hardwired to 1 to indicate the presence of a configuration register.
CONFIG = 1 There is a configuration register.
CONFIG = 0 There is no configuration register.
silicon errata
A description of known silicon errata for TI380PCIA devices stamped with the identifier “TI380PCIAPCM”
follows.
ID 380PCI20001—description
When the TI380PCIA is DMAing data to or from host memory, there is a very narrow window during which
back-to-back DIO reads or writes initiated by the host may conflict with the DMA. When the TI380PCIA is
DMAing data between host memory and the TI380C2x^†, if the host initiates a DIO access to the TI380PCIA,
then the TI380PCIA issues a retry to the host. The TI380PCIA then halts the DMA transfer between the
TI380C2x^† and the TI380PCIA. When the host retries the DIO access, it is allowed to complete successfully
and the TI380PCIA then permits the pending DMA to restart. If the host attempts a second DIO access within
one PCI cycle of completion of the successful DIO access (that is, if the host asserts the PCI bus FRAME signal
one PCI cycle after the completion of the previous successful DIO), then the second DIO access conflicts with
the restarting of the DMA, resulting in a data corruption of the DIO. In such a case, the second DIO read or write
data is replaced with the DMA address. Note that after the conflict, the DMA resumes successfully.
ID 380PCI20001—work-arounds
D Establish a handshake within driver software such that DIO accesses cannot take place during DMA
transfers.
or
D Ensure that back-to-back DIO accesses never take place within one PCI clock cycle.
† _{TI380C3x devices can be used with TI380PCIA in the same way as TI380C2x devices.}
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