TI380PCIA Datasheet, PDF (32/40 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS™
SPWS035 – JUNE 1997
ID 380PCI20002—description
When the TI380PCIA is requesting mastership of the PCI bus for a multicycle access prior to gaining control
of the PCI bus, the TI380PCIA may misinterpret assertion of the PCI STOP signal, destined for another target
on the PCI bus, and temporarily deassert its PCI REQ signal. The TI380PCIA reasserts the REQ signal when
STOP is deasserted. The deassertion of the REQ signal does not impact data integrity, but may slightly increase
the time taken for the TI380PCIA to achieve master control of the PCI bus. (After the TI380PCIA gains control
of the PCI bus, the master transaction completes without further disruption.) The impact of this behavior is
system-specific and depends upon the level of activity on the PCI bus STOP signal.
ID 380PCI20003—description
If the TI380PCIA experiences a soft reset due to a one-to-zero transition on the bus master bit (bit 2 of the
command register), or setting the software reset bit in the MISCCTRL register, the contents of the MIN_GNT
or MAX_LAT configuration registers are reset from the values loaded in from the serial EEPROM to the
hardwired default values for these registers. Note that host software can read the values for the MIN_GNT and
MAX_LAT registers that are stored in the EEPROM by means of the EEPROM interface register in TI380PCIA
configuration space, but these values cannot be written into the MIN_GNT and MAX_LAT registers by the host
because the two registers are defined as read-only configuration registers. Certain PCI BIOS software may
cause the TI380PCIA to perform a soft reset after power-up during the operating system boot process. In the
systems, the values in the MIN_GNT and MAX_LAT registers always appear to be the hardwired default values.
ID 380PCI20003—work-arounds
The contents of the MIN_GNT and MAX_LAT registers can be restored by asserting the TI380PCIA’s PCI reset
pin (RST), which causes the TI380PCIA to reload the contents of the EEPROM.
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