TI380PCIA Datasheet, PDF (19/40 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS™
SPWS035 – JUNE 1997
SIF behavior as a SIF master
The TI380PCIA SIF logic masters the TI380C2x^† system interface to translate signals from the PCIIF into
TI380C2x^† control signals and relays TI380C2x^† return signals to the PCIIF.
SIF behavior as a slave
The SIF acts as a slave when the TI380C2x^† is engaged in DMA operations. During DMA transfers, other PCI
masters can access the TI380C2x^† DIO registers. The TI380PCIA retries all accesses from the PCI bus while
posting a preempt to the TI380PCIA SIF. When the TI380PCIA SIF receives the preempt, it signals the
TI380C2x^† to relinquish the SIF bus at the earliest opportunity and does not grant the TI380C2x^† the SIF bus
until the preempt is removed.
FIFO control
The 64-byte FIFO serves to reduce the bandwidth demand on the PCI bus from the TI380PCIA. It is used only
when the TI380C2x^† is functioning as a PCI bus master during DMA accesses.
FIFO operation (write cycles)
The TI380PCIA BIF checks the status cycles on the TI380C2x^† local bus. When the TI380PCIA detects a status
code that indicates the start of a DMA write from the TI380C2x^† to the host computer, the TI380PCIA
immediately initiates a DIO read of the DMALEN register in the TI380C2x^†. When the DMALEN register has
been read, the TI380PCIA grants the TI380C2x^† control of the SIF bus and the DMA write can proceed.
The DMALEN register is not read again until the next DMA transaction starts. During DMA write cycles from
the TI380C2x^†, the TI380PCIA stores one cache line or 60 bytes in the FIFO before requesting the PCI bus.
It drives data on the PCI bus as long as it has sufficient data in the FIFO or until it loses the PCI bus. The FIFO
control requests the PCI bus under the following conditions:
D A full cache line is available for writing and the DMA address is aligned on a cache boundary. The PCI bus
cycle is a write-and-invalidate cycle.
D The TI380C2x^† relinquishes control of the SIF bus because of completion of a DMA write from the
TI380C2x^† with DMA data in the TI380PCIA FIFO. If the quantity of data in the TI380PCIA FIFO is greater
than or equal to the cache line size and the DMA address is aligned on a cache line boundary, the PCI cycles
are write-and-invalidates. If the quantity of data in the TI380PCIA FIFO is less than the cache line size or
the DMA address is not aligned on a cache line boundary, the PCI cycles are memory writes.
D A full 32-bit word is available for the PCI bus and the cache line size is zero.
If the host attempts a DIO access during a DMA transfer between the TI380C2x^† and the host, the TI380PCIA
signals the TI380C2x^† to pause the DMA transfer. When the TI380PCIA regains control of the SIF bus, the DIO
access from the host is allowed to complete, and then the TI380PCIA allows the DMA transfer to restart and
run to completion. The TI380PCIA signals the host to retry the DIO access until the TI380PCIA gains control
of the SIF bus and can allow the DIO access to complete. In the case of a DMA write from the TI380C2x^† to
the host (which is almost complete), the TI380PCIA can give up control of the SIF bus prior to transferring the
last data from the FIFO to the host. If the host initiates a DIO access at this time, the DIO access is allowed to
complete immediately, that is, before the FIFO empties.
FIFO operation (read cycles)
The TI380PCIA BIF checks the status cycles on the TI380C2x^† local bus. When the TI380PCIA detects a status
code that indicates the start of a DMA read by the TI380PCIA from the host computer, the TI380PCIA
immediately initiates a DIO read of the DMALEN register in the TI380C2x^†. When the DMALEN register has
been read, the TI380PCIA grants the TI380C2x^† control of the SIF bus, and the DMA read can proceed. The
DMALEN register is not read again until the next DMA transaction starts. The TI380PCIA then requests the PCI
bus and begins filling the FIFO. As data is available, it is provided to the TI380C2x^†. The TI380PCIA counts the
† _{TI380C3x devices can be used with TI380PCIA in the same way as TI380C2x devices.}
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