TI380PCIA Datasheet, PDF (27/40 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS™
SPWS035 – JUNE 1997
miscellaneous control register (MISCCTRL) — configuration space DWORD address (0x40) (continued)
Bit 10: Connector. The Connector bit indicates the type of connector in use. The value of this bit is present on
pin DB9 / UTP of the TI380PCIA. TI2000 drivers do not use this bit currently. However, it must always be read
as 0 if it is not implemented in adapter logic. Upon reset, this bit is 0.
1 = D-Shell (DB9 )
0 = UTP /10BaseT
Bits 11 – 15: Reserved. These bits are read as 0x09.
Bit 16: Sleep. Setting this bit to a 1 causes the SBCLK output from the TI380PCIA to be driven to a steady high
state. The TI380PCIA’s SBCLK output is used as the SBCLK input to the TI380C2x^†. Holding the sleep bit high
causes the TI380C2x^† to suspend operations and go into power-saving mode. When this bit changes from a
1 to 0, the SBCLK returns to normal operation. This bit is set to 0 on reset.
Bit 17: Expansion ROM address mode, 14/ 16. This bit indicates to the ROMIF that it should either use full 16-bit
addressing or support the TI2000 paging protocol. When using TI2000 paging, the ROMIF uses the least
significant 14 bits of the 16-bit ROM address, and the most significant two bits are provided by an internal
TI380PCIA page register. This bit is set to 0x0 after reset, indicating full 16-bit mode.
Bit 18: Reserved. This bit is reserved and is set to zero during reset by the TI380PCIA. This bit is read as zero
and must always be zero.
Bits 19 – 20: SBCLK divide ratio. These bits specify the relationship between the PCI clock and the TI380C2x^†
SBCLK (see Table 7). After reset, these bits are set to 0x1 (PCLK/2).
Table 7. SBCLK Divide-Ratio Bits
BIT 20
0
0
1
1
BIT 19
0
1
0
1
SBCLK FREQUENCY
PCLK / 1
PCLK / 2
PCLK / 3
PCLK / 4
Bits 21 – 27: Reserved
Bit 28: Address parity error. The address parity error bit is set to 1 when the TI380PCIA detects an
address-parity error when acting as a PCI slave. This bit is set to 0 after reset.
Bit 29: Target-reported parity error. The target-reported parity error bit is set to 1 when the TI380PCIA receives
a data-parity error (that is, it receives PERR during a master write and / or it detects a parity error during master
read). This bit is set to 0 after reset.
Bit 30: Retry count expired. The retry count expired bit is set to 1 when the TI380PCIA has exceeded the
maximum retry count with a master transaction. This bit is set to 0 after reset.
Bit 31: Software reset. Software reset is a programmable reset. Setting this bit to a 1 causes the SRESET output
to pulse low for a minimum of 14 µs and results in a hard reset to the LAN subsystem. (This function is provided
primarily for hardware and driver-software debug purposes.) This bit is set to 0 after reset. When set to 1, this
bit resets itself to 0 after four PCI clock cycles.
† _{TI380C3x devices can be used with TI380PCIA in the same way as TI380C2x devices.}
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