TI380PCIA Datasheet, PDF (34/40 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS™
SPWS035 – JUNE 1997
PARAMETER MEASUREMENT INFORMATION
Outputs are driven to a minimum high-logic level of 2.4 V and to a maximum low-logic level of 0.6 V. These levels
are compatible with TTL devices.
Output transition times are specified as follows: For a high-to-low transition on either an input or output signal,
the level at which the signal is said to be no longer high is 2 V, and the level at which the signal is said to be low
is 0.8 V. For a low-to-high transition, the level at which the signal is said to be no longer low is 0.8 V, and the
level at which the signal is said to be high is 2 V, as shown in Figure 18.
The rise and fall times are not specified but are assumed to be those of standard TTL devices, which are typically
1.5 ns.
2 V (High)
0.8 V (Low)
Figure 18. Output Transition Levels
test measurement
The test load circuit shown in Figure 19 represents the programmable load of the tester pin electronics used
to verify timing parameters of TI380PCIA output signals.
IOL
Tester Pin
Electronics
VLOAD
Output
Under
Test
CT
IOH
Where:
I_OL = 2.0 mA DC-level verification (all outputs)
I_OH = 400 µA (all outputs)
V_LOAD = 1.5 V typical DC-level verification
0.7 V typical timing verification
C_T = 65 pF typical load circuit capacitance and includes probe and jig capacitance
Figure 19. Test Load Circuit
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