TI380PCIA Datasheet, PDF (5/40 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS™
SPWS035 – JUNE 1997
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O†
DESCRIPTION
VDD
10
22
34
37
46
50
58
70
I 5 - V supply. These pins must be attached to the common system power supply plane.
79
82
94
106
118
130
142
SYSTEM INTERFACE (SIF)‡
SADH0 /ROMA08 113
SADH1 /ROMA09 114
System address / data bus — high byte. These lines make up the most significant byte (MSByte) of each
TI380C2x§ address word (32-bit address bus) and data word (16-bit data bus). The most significant bit
SADH2 /ROMA10 115
(MSB) is SADH0, and the least significant bit (LSB) is SADH7.
SADH3 /ROMA11
SADH4 /ROMA12
116
117
I / O _{Address-multiplexing bits 31 – 24 and bits 15 – 8¶}
SADH5 /ROMA13 119
Data-multiplexing bits 15 – 8¶
SADH6 /ROMA14 120
During accesses to the ROM address space from the PCI bus, these lines provide the eight most
SADH7 /ROMA15 121
significant address bits to the ROM.
SADL0 /ROMD7
SADL1 /ROMD6
SADL2 /ROMD5
SADL3 /ROMD4
SADL4 /ROMD3
SADL5 /ROMD2
SADL6 /ROMD1
SADL7 /ROMD0
132
System address / data bus — low byte. These lines make up the least significant byte (LSByte) of each
133
address word (32-bit address bus) and data word (16-bit data bus). The MSB is SADL0, and the LSB
134
is SADL7. These address lines also make up the ROM address.
135
137
I / O _{Address-multiplexing bits 23 – 16 and bits 7 – 0¶}
138
Data-multiplexing bits 7 – 0¶
139
During accesses to the ROM address space from the PCI bus, these lines transfer data from the ROM
140
to the TI380PCIA.
SALE
143
I
System-address latch-enable. SALE is the enable pulse used to latch the 16 LSBs of the address
externally from the SADH0 – SADH7 and SADL0 – SADL7 buses at the start of the DMA cycle.
SAS
System-memory address strobe. SAS is an active-low address strobe that is an output during DIO and
an input during DMA.#
2
I/O
H = Address not valid
L = Address is valid and a transfer operation is in progress
SBCLK
141
O
SIF bus clock. The TI380C2x§ requires SBCLK to synchronize its bus timings for all DMA transfers
(see Note 1).
† _{I = in, O = out}
‡ _{The TI380PCIA SIF pin names correspond to a subset of the system interface pins on a TI380C2x§. See the TI380C2x§ data sheets for more}
information on individual pins. Like-named pins on the TI380PCIA and TI380C2x§ system interfaces are intended to be connected to each
other.
§ _{TI380C3x devices can be used with TI380PCIA in the same way as TI380C2x devices.}
¶ _{Typical bit-ordering for Intel™ and Motorola™ processor buses}
# _{The signal connecting this pin to the TI380C2x§ also should be connected to a 4.7-kΩ pullup resistor.}
|| _{The TI380PCIA BIF pin names correspond to a subset of the local memory bus interface pins on a TI380C2x§. Like-named pins on the two}
devices are intended to be connected to each other. Consult the TI380C2x§ data sheets for more information on individual pins.
NOTE 1: The TI380PCIA allows driver software to set SBCLK output to a steady high state. This signal is driven to a steady high state during
power-down operations.
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