TI380PCIA Datasheet, PDF (12/40 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS™
SPWS035 – JUNE 1997
architecture
The major blocks of the TI380PCIA, illustrated in Figure 2, include the PCI interface (PCIIF ), TI380C2x^†
interface (SIF ), ROM interface (ROMIF ), serial EEPROM interface (EIF), and burned-in address emulation
interface (BIF). The functionality of each block is described in the following sections.
PCI interface (PCIIF )
The PCIIF block contains all logic needed to interact with the PCI bus and allows the TI380PCIA to assume the
role of bus master or slave. This block controls all communication between the TI380PCIA and the PCI bus.
All signals entering the PCIIF, as well as signals generated within the PCIIF, are synchronous to the PCLK signal.
The TI380PCIA also checks and generates parity for data presented on the PCI bus at the PCIIF.
The PCIIF generates and responds to the PCI cycles listed in Table 1.
Table 1. PCI Interface Logic
TI380PCIA CAN GENERATE:
Memory read line
Memory write and invalidate
Memory write
TI380PCIA RESPONDS TO:
I / O reads and writes
Configuration reads and writes
All types of memory reads and writes
The TI380PCIA asserts slave-initiated termination, if the initiator exceeds one data-phase transfer.
address decode
The TI380PCIA uses only the most significant 27 address bits present in AD31 – AD00 to decode an access
directed at the TI380PCIA for a TI380C2x^† DIO access, and the most significant 16 bits for a ROM access. The
TI380PCIA’s base address selects a block of eight contiguous 32-bit memory or I / O locations for DIO access
or 64K bytes of address space for ROM access. Access to each register within the selected memory, I / O, or
configuration space is uniquely decoded. The decode logic returns DEVSEL as a medium-latency device.
The PCIIF logic generates control signals that propagate either to configuration registers, the SIF, ROMIF, or
EIF within the TI380PCIA. The address and command / byte-enables are valid and sustained throughout each
PCI cycle. Configuration registers can be accessed through configuration cycles when the TI380PCIA’s address
is decoded.
address/data-parity checking and generation
The PCIIF checks and generates parity for addresses during bus master operations and for data during master
and slave operations. If the PCIIF encounters SERR two PCLKs after the address phase when it is mastering
the PCI bus, it terminates its transaction immediately and regains control of the TI380C2x^† SIF. If the PCIIF
detects any address error (even if not selected) or data parity error (only when selected) while operating as a
PCI slave, or if it detects a data parity error while operating as a PCI bus master, it pulses PERR and sets bit
15 in the status register to 1. Bus transactions causing the parity error are otherwise ignored by the LAN
subsystem. Any bus-mastering transaction that encounters a parity error is aborted by the TI380PCIA. This
detection also prevents future bus master cycles from occuring until a reset occurs.
The TI380PCIA performs a bus master cycle when bus-mastering is enabled and the TI380C2x^† requests the
SIF bus.
The supported PCI master cycles are:
D Memory write
D Memory read line
D Memory write and invalidate
† _{TI380C3x devices can be used with TI380PCIA in the same way as TI380C2x devices.}
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