TI380PCIA Datasheet, PDF (29/40 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS™
SPWS035 – JUNE 1997
TI380PCIA interface control register—configuration space DWORD address (0x54)
Figure 16 shows the layout of the interface control register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits 0 – 15:
Reserved; may not
be read as zero.
Bit 16:
Automatic
Software-Reset
Bits 17 – 31:
Reserved; may not
be read as zero.
Figure 16. Interface Control Register Layout
Bits 00 – 15: Reserved; may not be read as zero
Bit 16: Automatic software-reset. The automatic software-reset controls the impact of writing a zero to the bus
master bit (bit 2) in the TI380PCIA command register of DWORD address 0x04. When this bit is set to zero,
the TI380PCIA resets itself if the host processor causes a transition from one to zero of the bus master bit. When
bit 16 is set to one, the TI380PCIA does not reset itself when the host processor causes a transition from one
to zero of the bus master bit.
Typically, in personal computer (PC) systems, the TI380PCIA automatic software-reset bit is set to a default
value of zero. In a PC system, when a CTRL-ALT-DEL is issued from the keyboard, the PCI bus does not receive
a reset. A TI380PCIA bus master in the middle of a DMA transaction when the CTRL-ALT-DEL is issued can
be left in an unknown state. In this condition, the bus master could perform unexpected memory accesses to
the host after the TI380PCIA device is enabled by the PCI BIOS during the boot process.
To eliminate this problem, the automatic software-reset bit must be left set to the default value of zero. The action
of clearing the bus master bit in the TI380PCIA control register (which is a direct consequence of issuing the
CTRL-ALT-DEL) also automatically resets the TI380PCIA and clears any pending DMA transactions. The reset
induced by clearing the TI380PCIA bus master bit is the same as the software-reset that takes place when
bit 31 of the TI380PCIA MISCCTRL register is set to a one.
Bits 17 – 31: Reserved; may not be read as zero
TI2000 configuration register
The configuration register is defined in I / O space at offset 0xE – 0xF from the I/O base address (given in BASE0).
Figure 17 shows the layout of the TI2000 configuration register.
15
14
Config
rsvd
rsvd = reserved
13
12
11
10
9
8
7
43
0
rsvd
DEDMACTL INST8 Connector Speed Topology
INT
DMA
Figure 17. TI2000 Configuration Register Layout
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