SDA5250 Datasheet, PDF (97/143 Pages) Siemens Semiconductor Group – TVTEXT 8-Bit Microcontroller

SDA 525x
Figures 32 and 34 show a functional diagram of the serial port in modes 2 and 3 and
associated timings. The receive portion is exactly the same as in mode 1. The transmit
portion differs from mode 1 only in the 9th bit of the transmit shift register.
Transmission is initiated by any instruction that uses SBUF as a destination register. The
“write-to- SBUF” signal also loads TB8 into the 9th bit position of the transmit shift
register and flags the TX- control unit that a transmission is requested. Transmission
commences at the beginning of the machine cycle following the next rollover in the
divide-by-16 counter (thus, the bit times are synchronized to the divide-by-16 counter,
not to the “write-to-SBUF” signal).
The transmission begins with activation of SEND, which puts the start bit to TxD. One bit
time later, DATA is activated which enables the output bit of the transmit shift register to
TxD. The first shift pulse occurs one bit time after that. The first shift clocks a 1 (the stop
bit) into the 9th bit position of the shift register. Thereafter, only zeros are clocked in.
Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is
at the output position of the shift register, then the stop bit is just left of the TB8, and all
positions to the left of that contain zeros.
This condition flags the TX-control unit to do one last shift and then deactivate SEND
and set Tl. This occurs at the 11th divide-by-16 rollover after “write-to-SBUF”.
Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is
sampled at a rate of 16 times whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is immediately reset, and 1FF_H is written
to the input shift register.
At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value
of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. If
the value accepted during the first bit time is not 0, the receive circuits are reset and the
unit goes back looking for another 1-to-0 transition. If the start bit proves valid, it is shifted
into the input shift register, and reception of the rest of the frame will proceed. As data
bits come in from the right, 1 s shift out to the left. When the start bit arrives at the
leftmost position in the shift register (which in modes 2 and 3 is a 9-bit register), it flags
the RX-control block to do one last shift, load SBUF and RB8, and set Rl. The signal to
load SBUF and RB8, and to set Rl, will be generated if, and only if, the following
conditions are met at the time the final shift pulse is generated:
1. Rl = 0, and
2. either SM2 = 0 or the received 9th data bit = 1
If either of these two conditions is not met, the received frame is irretrievably lost, and Rl
is not set. If both conditions are met, the received 9th data bit goes into RB8, the first 8
data bits go into SBUF. One bit time later, no matter whether the above conditions are
met or not, the unit goes back looking for a 1-to-0-transition at the RxD input.
Note that the value of the received stop bit is irrelevant to SBUF, RB8 or Rl.
Semiconductor Group
97
1998-04-08