SDA5250 Datasheet, PDF (88/143 Pages) Siemens Semiconductor Group – TVTEXT 8-Bit Microcontroller

SDA 525x
Watchdog Timer Control Bits
Watchdog Timer Reload
Register
WDTREL
SFR-Address 86_H
Default after reset: 00_H
(MSB)
(LSB)
WDTREL.7 WDTREL.6 WDTREL.5 WDTREL.4 WDTREL.3 WDTREL.2 WDTREL.1 WDTREL.0
WDTREL.7
WDTREL.0 -
WDTREL.6
Prescaler bit. When set, the watchdog is clocked through an
additional divide-by-64 prescaler.
Seven bit reload value for the high-byte of the watchdog timer.
This value is loaded to the WDT when a refresh is triggered by
a consecutive setting of bits WDT and SWDT.
Watchdog Timer Control
Register
Default after reset: 00_H
(MSB)
WDTS SWDT
–
WDCON
–
–
SFR-Address A7_H
(LSB)
–
–
–
WDTS
Watchdog timer reset flag. If bit WDTS is ‘1’ after reset, the
reset has been initiated by the watchdog timer. After external
reset, WDTS is reset to ‘0’.
SWDT
Watchdog timer start flag. Set to activate the watchdog timer.
When directly set after setting WDT, a watchdog timer refresh
is performed.
WDCON.0 - WDCON.5 Reserved.
Semiconductor Group
88
1998-04-08