SDA5250 Datasheet, PDF (62/143 Pages) Siemens Semiconductor Group – TVTEXT 8-Bit Microcontroller

SDA 525x
Table 13
Special Function Register Overview (cont’d)
Special Function Register
Description
Symbolic
Name
Address
Location
(hex.)
Address
Location
(dec.)
Bit Address
MSB … LSB
(hex.)
Initial
Value after
Reset
(hex./bin.)
Display Control Registers
Horizontal Delay
Vertical Delay
Transparent Control
Mode 1 Register
Mode 2 Register
Sync Interrupt Request Reg.
Language Control
Cursor Column Position
Cursor Row Position
Display Timing Control
Sandcastle Control
Display Mode
DHD
C3
DVD
C4
DTCR
C5
DMODE1 C6
DMODE2 C7
TTXSIR C8
LANGC C9
DCCP
CA
DCRP
CB
DTIM
CC
SCCON CE
DMOD
D6
195
–
00
196
–
00
197
–
00
198
–
00
199
–
00
200
CF - C8
00
201
–
00
202
–
00
203
–
00
204
–
00
206
–
00
214
–
x0
6.3.3
Interrupt System
External events and the real-time on-chip peripherals require CPU-service
asynchronous to the execution of any particular section of code. To couple the
asynchronous activities of these functions to normal program execution, a sophisticated
multiple-source, four-priority-level, nested interrupt system is provided. Interrupt
response delay ranges from 0,89 µs to 2.33 µs when using an 18-MHz clock (see
Chapter “Advanced Function Register” on page 115).
6.3.3.1 Interrupt Sources
The processor acknowledges interrupt requests from seven sources: two from external
sources via the INT0 and INT1 pins, one from each of the two internal counters, one from
the serial I/O-port, one from teletext sync signals and one from the analog digital
converter. Each of the seven sources can be assigned to either of four priority levels and
can be independently enabled and disabled. Additionally, all enabled sources can be
globally disabled or enabled.
Interrupts result in a transfer of control to a new program location. Each interrupt vectors
to a separate location in program memory for its service program. The program servicing
the request begins at this address. The starting address (interrupt vector) of the interrupt
service program for each interrupt source is shown in the Table 14.
Semiconductor Group
62
1998-04-08