SDA5250 Datasheet, PDF (74/143 Pages) Siemens Semiconductor Group – TVTEXT 8-Bit Microcontroller

SDA 525x
6.3.4.3 Interrupt Task Function
The processor records the active priority level(s) by setting internal flip-flop(s). Each
interrupt level has its own flip-flop. The flip-flop corresponding to the interrupt level being
serviced is reset when the processor executes a RETI-instruction.
The sequence of events for an interrupt is:
– A source provokes an interrupt by setting its associated interrupt request bit to let the
processor know an interrupt condition has occurred.
– The interrupt request is conditioned by bits in the interrupt enable and interrupt priority
registers.
– The processor acknowledges the interrupt by setting one of the four internal “priority-
level active” flip-flops and performing a hardware subroutine call. This call pushes the
PC (but not the PSW) onto the stack and, for some sources, clears the interrupt
request flag.
– The service program is executed.
– Control is returned to the main program when the RETI-instruction is executed. The
RETI- instruction also clears one of the internal “priority-level active” flip-flops.
The interrupt request flags IE0, IE1, TF0 and TF1 are cleared when the processor
transfers control to the first instruction of the interrupt service program. The RI/TI,
DVIRST, DHIRST, EVENST, LIN24ST, AVIRST, AHIRST and IADC-interrupt request
flags must be cleared as part of the respective interrupt service program.
6.3.4.4 Response Time
The highest-priority interrupt request gets serviced at the end of the instruction in
progress unless the request is made in the last seven (CDC=0) oscillator periods of the
instruction in progress. Under this circumstance, the next instruction will also execute
before the interrupt's subroutine call is made.
If a request is active and conditions are right for it to be acknowledged, a hardware
subroutine call to the requested service routine will be the next instruction to be
executed. The call itself takes two cycles. Thus, a minimum of three complete machine
cycles elapse between activation of an external interrupt request and the beginning of
execution of the first instruction of the service routine. If the instruction in progress is not
in its final cycle, the additional wait time cannot be more than 3 cycles, since the longest
instructions (MUL and DIV) are only 4 cycles long, and if the instruction in progress is
RETI or an access to IE or IP0 and IP1, the additional wait time cannot be more than 5
cycles (a maximum of one more cycle to complete the instruction in progress, plus 4
cycles to complete the next instruction if the instruction is MUL or DIV). Thus, in a single-
interrupt system, the response time is always more than 3 cycles and less than 8 cycles
(approximately 2.33 µs at 18-MHz operation). Note, that a machine cycle can consist of
12 oscillator periods (CDC = 1) or only six oscillator periods (CDC = 0) (see
Chapter “Advanced Function Register” on page 115). Examples of the best and
worst case conditions are illustrated in Table 19.
Semiconductor Group
74
1998-04-08