SDA5250 Datasheet, PDF (70/143 Pages) Siemens Semiconductor Group – TVTEXT 8-Bit Microcontroller

SDA 525x
Interrupt Priority Register IP0 and IP1
Interrupt Priority Register
Default after reset: 00_H
(MSB)
–
IP0.6 IP0.5
IP0
IP0.4 IP0.3
SFR-Address A9_H
IP0.2
IP0.1
(LSB)
IP0.0
Interrupt Priority Register
Default after reset: 00_H
(MSB)
–
IP1.6 IP1.5
IP1
IP1.4 IP1.3
SFR-Address AA_H
IP1.2
IP1.1
(LSB)
IP1.0
Corresponding bit-locations in both registers are used to set the interrupt priority level of
an interrupt.
Table 16
IP1.X
0
0
1
1
IP0.X
0
1
0
1
Function
Set priority level 0 (lowest)
Set priority level 1
Set priority level 2
Set priority level 3 (highest)
Table 17
Bit
IP1.0 / IP0.0
IP1.1 / IP0.1
IP1.2 / IP0.2
IP1.3 / IP0.3
IP1.4 / IP0.4
IP1.5 / IP0.5
IP1.6 / IP0.6
Corresponding Interrupt
IE0
TF0
IE1
TF1
RI/TI
DVIRST/ DHIRST/ EVENST/ LIN24ST/AVIRST/AHIRST
IADC
Setting/clearing a bit in the IP-registers establishes its associated interrupt request
priority level. If a low-priority level interrupt is being serviced, a higher-priority level
interrupt will interrupt it. However, an interrupt source cannot interrupt a service program
of the same or higher priority level.
Semiconductor Group
70
1998-04-08