SDA5250 Datasheet, PDF (115/143 Pages) Siemens Semiconductor Group – TVTEXT 8-Bit Microcontroller

SDA 525x
ADC-Data Register ADDAT
ADC-Data Register
Default after reset: undefined
(MSB)
AD7
AD6
AD5
ADDAT
AD4
AD3
SFR-Address D9_H
AD2
AD1
(LSB)
AD0
AD (7-0)
8-Bit Analog Data Value
6.3.13 Advanced Function Register
Advanced Function Register
Default after reset: 00xxxxxxB
(MSB)
CDC
WDT
0
AFR
0
0
SFR-Address A6_H
(LSB)
0
0
0
CDC
Clock divider control bit. If set, the clock divider is on. The
internal clock frequency is half the external oscillator
frequency. If cleared, the clock divider is off. The internal clock
frequency is equal to the external oscillator frequency. This
feature can be used to reduce power dissipation by reducing
the internal clock frequency by a factor of two.
WDT
See Chapter “Watchdog Timer” on page 87.
AFR.0 – AFR.5
Reserved, always to be written with ‘0’.
The machine cycle time is controlled by bit CDC too. For CDC = 1 a machine cycle
consists of 12 oscillator cycles and for CDC = 0 of six oscillator cycles (see Figure 14).
Semiconductor Group
115
1998-04-08