SDA5250 Datasheet, PDF (46/143 Pages) Siemens Semiconductor Group – TVTEXT 8-Bit Microcontroller

SDA 525x
Watchdog Timer
For software- and hardware security, a watchdog timer is supplied, which resets the
processor, if not cleared by software within a maximum time period.
Pulse Width Modulation Unit
Up to six lines of port 1 may be used as 8-bit PWM-outputs and two lines of port 1 may
be used as 14-bit PWM-output. The PWM-logic is controlled by registers
PWCOMP0 … 7, PWCL, PWCH, PWME, PWEXT6, PWEXT7 (see Chapter “Pulse
Width Modulation Unit (PWM)” on page 106).
Capture Compare Timer
For easy decoding of infrared remote control signals, a dedicated timer is available (see
Chapter “Capture Compare Timer” on page 90).
6.3.1.2 CPU-Timing
Timing generation is completely self-contained, except for the frequency reference
which can be a crystal or external clock source. The on-board oscillator is a parallel anti-
resonant circuit. There is a divide-by-6 internal timing which leads to a minimum
instruction cycle of 0.33 µs with an 18-MHz crystal. The XTAL2-pin is the output of a
high-gain amplifier, while XTAL1 is its input. A crystal connected between XTAL1 and
XTAL2 provides the feedback and phase shift required for oscillation.
A machine cycle consists of 6 oscillator periods (software selectable). Most instructions
execute in one cycle. MUL (multiply) and DIV (divide) are the only instructions that take
more than two cycles to complete. They take four cycles.
To reduce the power consumption, the internal clock frequency can be divided by two,
which slows down the processor operations.
This slow down mode is entered by setting SFR-Bit CDC in register AFR.
Note: All timing values and diagrams in this specification refer to an inactivated clock
divider (CDC = 0).
Note: Slow down mode should only be used if teletext reception and the display are
disabled. Otherwise processing of the incoming text data might be incomplete and
the display structure will be corrupted.
Semiconductor Group
46
1998-04-08