SDA5250 Datasheet, PDF (82/143 Pages) Siemens Semiconductor Group – TVTEXT 8-Bit Microcontroller

SDA 525x
Timer/Counter 1: Mode Selection
Timer/counter 1 can also be configured in one of four modes, which are selected by its
own bitpairs (M1, M0) in TMOD-register.
The serial port receives a pulse each time that timer/counter 1 overflows. This pulse rate
is divided to generate the transmission rate of the serial port.
Modes 0 and 1 are the same as for counter 0.
– Mode 2
The “reload” mode is reserved to determine the frequency of the serial clock signal (not
implemented).
– Mode 3
When counter 1's mode is reprogrammed to mode 3 (from mode 0, 1 or 2), it disables
the increment counter. This mode is provided as an alternative to using the TR1 bit (in
TCON-register) to start and stop timer/counter 1.
Configuring the Timer/Counter Input
The use of the timer/counter is determined by two 8-bit registers, TMOD (timer mode)
and TCON (timer control), as shown on page 83 and 84. The input to the counter
circuitry is from an external reference (for use as a counter), or from the on-chip oscillator
(for use as a timer), depending on whether TMOD's C/T-bit is set or cleared,
respectively. When used as a time base, the on-chip oscillator frequency is divided by
twelve or six (see Figure 25, 26 and 26) before being used as the counter input. When
TMOD's GATE bit is set (1), the external reference input (T1, T0) or the oscillator input
is gated to the counter conditional upon a second external input (INT0), (INT1) being
high. When the GATE bit is zero (0), the external reference, or oscillator input, is
unconditionally enabled. In either case, the normal interrupt function of INT0 and INT1
is not affected by the counter's operation. If enabled, an interrupt will occur when the
input at INT0 or INT1 is low. The counters are enabled for incrementing when TCON's
TR1 and TR0 bits are set. When the counters overflow, the TF1 and TF0 bits in TCON
get set, and interrupt requests are generated.
The counter circuitry counts up to all 1's and then overflows to either 0's or the reload
value. Upon overflow, TF1 or TF0 is set. When an instruction changes the timer's mode
or alters its control bits, the actual change occurs at the end of the instruction's
execution.
The T1 and T0 inputs are sampled near the falling-edge of ALE in the tenth, twenty-
second, thirty-fourth and forty-sixth oscillator periods of the instruction-in-progress
(CDC=1). Thus, an external reference's high and low times must each have a minimum
duration of twelve oscillator periods for CDC = 1 or six oscillator periods for CDC = 0.
There is a twelve (CDC = 1) or six (CDC = 0) oscillator period delay from the time when
a toggled input (transition from high to low) is sampled to the time when the counter is
incremented.
Semiconductor Group
82
1998-04-08