SDA5250 Datasheet, PDF (95/143 Pages) Siemens Semiconductor Group – TVTEXT 8-Bit Microcontroller

SDA 525x
6.3.10.3 More about Mode 0
Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are
transmitted/ received: 8 data bits (LSB first).
Figure 28 shows a simplified functional diagram of the serial port in mode 0, and
associated timing.
Transmission is initiated by any instruction that uses SBUF as a destination register. The
“write-to SBUF” signal also loads a 1 into the 9th bit position of the transmit shift register
and tells the TX-control block to commence a transmission. The internal timing is such
that one full machine cycle will elapse between “write-to-SBUF” and activation of SEND.
SEND enables the output of the shift register to the alternate output function line of P3.6,
and also enables SHIFT CLOCK to the alternate output function, line of P3.7. At the end
of every machine cycle in which SEND is active, the contents of the transmit shift register
is shifted one position to the right.
As data bits shift out to the right, zeros come in from the left. When the MSB of the data
byte is at the output position of the shift register, then the 1 that was initially loaded into
the 9th position, is just left of the MSB, and all positions to the left of that contain zeros.
This condition flags the TX-control block to do one last shift and then deactivate SEND
and set Tl. Both of these actions occur in the 10th machine cycle after “write-to-SBUF”.
Reception is initiated by the condition REN = 1 and Rl = 0. At the end of the next
machine cycle, the RX-control unit writes the bits ‘1111 1110’ to the receive shift register,
and the next clock phase activates RECEIVE.
RECEIVE enables SHIFT CLOCK to the alternate output function line of P3.7. At the end
of every machine cycle in which RECEIVE is active, the contents of the Receive Shift
register are shifted one position to the left. The value that comes in from the right is the
value that was sampled at the P3.6 pin in the same machine cycle.
As data bits come in from the right, 1 s shift out to the left. When the 0 that was initially
loaded into the rightmost position arrives at the leftmost position in the shift register, it
flags the RX-control block to do one last shift and load SBUF. In the 10th machine cycle
after the write to SCON that cleared Rl, RECEIVE is cleared and Rl is set.
6.3.10.4 More about Mode 1
Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data
bits (LSB first) and a stop bit (1). On reception, the stop bit goes into RB8 in SCON.
The baud rate is determined by the timer 1 overflow rate.
Figure 30 shows a simplified functional diagram of the serial port in mode 1, and
associated timings for transmit and receive.
Transmission is initiated by any instruction that uses SBUF as a destination register. The
“write-to SBUF” signal also loads a ‘1’ into the 9th bit position of the transmit shift register
and flags the TX- control block that a transmission is requested. Transmission actually
Semiconductor Group
95
1998-04-08