SDA5250 Datasheet, PDF (112/143 Pages) Siemens Semiconductor Group – TVTEXT 8-Bit Microcontroller

SDA 525x
6.3.12 Analog Digital Converter
The controller provides an A/D-converter with the following features:
– 4 multiplexed input channels, which can also be used as digital inputs
– 8-bit resolution
– 8.89 to 28.4 µs conversion time for 18 MHz oscillator frequency
– Analog reference voltages supplied by pins V_DDA and V_SSA
The conversion time depends on the internal master clock, used by the ADC. The clock-
frequency of the internal ADC master clock is defined by the external quartz (oscillator
frequency f_OSC), the setting of bit CDC in the Advanced Function Register AFR of the
special function registers (SFR) (see Chapter “Advanced Function Register” on
page 115), and the setting of bit PSC in the ADC Control Register ADCON (SFR). Both
bits are software switches to activate or deactivate clock dividers by 2. The conversion
time further depends on the sample time, adjustable by bit STADC (ADC-Control
Register ADCON).
The conversion time can be calculated by:
t_conversion
=
(_---2_---²_----^×_----^S_---^T_----^A_---^D_----^C_-----+_-----4_---)_----×_-----3_---2_-----×_-----2_---^C_----^D_---^C_----×_-----2_----^P_---^S_---^C_-
f _OSC
For the conversion, the method of successive approximation via capacitor array is used.
There are three user-accessible special function registers: ADCON, ADDAT and DAPR.
Special function register ADCON is used to set the operation modes, to check the status
and to select one of four input channels. ADCON contains two mode bits. Bit ADM is
used to choose the single or continuous conversion method. In single conversion mode
(ADM = 0) only one conversion is performed after starting, while in continuous
conversion mode (ADM = 1) a new conversion is automatically started on completion of
the previous one. The busy flag BSY (ADCON.4) is automatically set when a conversion
is in progress. After completion of the conversion it is reset by hardware. This flag can
be read only, a write has no effect. MX0 and MX1 are used to select one of 4 A/D-
channels. With PSC a divide by two prescaler for the internal master clock of the ADC
can be activated. For PSC = 0 the internal chip-clock is used as master clock for the
ADC. For PSC = 1 the internal chip-clock is divided by two before being used as master
clock for the ADC. With bit STADC the sample time of the ADC can be varied. Bit
STADC = 0 selects the normal sample time (sample time of 2 ADC master clock cycles),
while for STADC = 1 the sample time is slowed down by a factor of 4 (sample time of 8
ADC master clock cycles) e.g. for high-impedance input signals.
The special function register ADDAT holds the converted digital 8-bit data result. The
data remains in ADDAT until it is overwritten by the next converted data. ADDAT can be
read or written under software control. A start of conversion is triggered by a write-to
DAPR instruction. The data written must be 00_H.
Semiconductor Group
112
1998-04-08