SDA5250 Datasheet, PDF (93/143 Pages) Siemens Semiconductor Group – TVTEXT 8-Bit Microcontroller

SDA 525x
Table 22
Serial Port Mode Selection
SM0
SM1 Mode Description
0
0
0
Shift Reg.
0
1
1
8-bit UART
1
0
2
9-bit UART
1
1
3
9-bit UART
Baud Rate (CDC = 0)
f_OSC/6
Variable
f_OSC/32, f_OSC/16
Variable
In all four modes, transmission is initiated by any instruction that uses SBUF as a
destination register. Reception is initiated in mode 0 by the condition Rl = 0 and
REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1.
The control, mode, and status bits of the serial port in special function register SCON are
illustrated on page 92.
6.3.10.1 Multiprocessor Communication
Modes 2 and 3 of the serial interface of the controller have a special provision for
multiprocessor communication. In these modes, 9 data bits are received. The 9th one
goes into RB8. Then comes a stop bit. The port can be programmed such that when the
stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature
is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor
communications is as follows.
When the master processor wants to transmit a block of data to one of the several
slaves, it first sends out an address byte which identifies the target slave. An address
byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data
byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte
however, will interrupt all slaves, so that each slave can examine the received byte and
see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to
receive the data bytes that will be coming. The slaves that weren't addressed leave their
SM2s set and go on about their business, ignoring the coming data bytes.
SM2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop
bit. In a mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a
valid stop bit is received.
Semiconductor Group
93
1998-04-08