SDA5250 Datasheet, PDF (16/143 Pages) Siemens Semiconductor Group – TVTEXT 8-Bit Microcontroller

SDA 525x
6
Functional Description
6.1
Acquisition
6.1.1
TTX/VPS Slicer
The slicer extracts horizontal and vertical sync information and TTX data from the CVBS
signal. The slicer includes an analog circuit for sync filtering and data slicing. Further
there are two analog PLLs for system clock generation for both TTX and VPS. Therefore
the slicer is able to receive both TTX and VPS in succeeding lines of a vertical blanking
interval. A third data-PLL shifts the phase of the system clock for data sampling. The
internal slicer timing signals are generated from the VPS-PLL.
6.1.2
Acquisition Hardware
The acquisition hardware transforms the sliced bit stream into a byte stream. A framing
code check follows to identify a TTX or VPS line. If the framing code error tolerance is
enabled then one-bit errors will be allowed.
For each line in the VBI in which a framingcode is detected, a maximum of 42 bytes
(VPS: 26 bytes) plus a status word are stored in the VBI-buffer. After framing code
detection a status word is generated which informs about the type of data received (TTX
or VPS) and the signal quality of the TV channel. Chapter “Acquisition Status Word”
on page 17 shows the format of this status word. The horizontal and vertical windows in
which TTX or VPS data are accepted and checked for framing code errors are generated
automatically. The VBI buffer data will be analyzed (Hamming, parity and acquisition) by
the microcontroller and stored in the dual port display RAM or the external RAM, if
selected. This analysis is repeated for every field.
Semiconductor Group
16
1998-04-08