SDA5250 Datasheet, PDF (87/143 Pages) Siemens Semiconductor Group – TVTEXT 8-Bit Microcontroller

SDA 525x
6.3.8
Watchdog Timer
To protect the systems against software upset, the user's program has to clear this
watchdog within a previously programmed time period. If the software fails to do this
periodical refresh of the watchdog timer, an internal hardware reset will be initiated. The
software can be designed so that the watchdog times out if the program does not work
properly.
The watchdog timer is a 15-bit timer, which is incremented by a count rate of either
f_CYCLE/2 or f_CYCLE/128. The latter is enabled by setting bit WDTREL.7. Note, that f_CYCLE
can be f_Quarz/12 for CDC = 1 or f_Quarz/6 for CDC = 0 (see Chapter “Advanced Function
Register” on page 115). Immediately after start, the watchdog timer is initialized to the
reload value programmed to WDTREL.0 – WDTREL.6. After an external reset register
WDTREL is cleared to 00_H. The lower seven bits of WDTREL can be loaded by software
at any time.
The watchdog timer is started by software by setting bit SWDT in special function
register WDCON (bit 6). If the counter is stopped, and WDTREL is loaded with a new
value, WDTH (high-byte of the watchdog timer) is updated immediately. WDTL (low-byte
of the watchdog timer) is always zero, if the counter is stopped. Once started the
watchdog timer cannot be stopped by software but can only be refreshed to the reload
value by first setting bit WDT (AFR.6) and by the next instruction setting SWDT
(WDCON.6). Bit WDT will automatically be cleared during the third machine cycle after
having been set. This double instruction refresh of the watchdog timer is implemented to
minimize the chance of an unintentional reset of the watchdog.
If the software fails to clear the watchdog in time, an internally generated watchdog reset
is entered at the counter state 7FFF_H. The duration of the reset signal then depends on
the prescaler selection. This internal reset differs from an external reset only in so far as
the watchdog timer is not disabled and bit WDTS (WDCON.7) is set. Bit WDTS allows
the software to examine from which source the reset was activated. The watchdog timer
status flag can also be cleared by software.
With WDTREL = 80_H and an oscillator frequency of 18 MHz the maximum time period is
about 0.7 s for CDC = 0 and about 1.4 s for CDC = 1.
Semiconductor Group
87
1998-04-08