K4J55323QF-GC Datasheet, PDF(9/49 Page) Samsung semiconductor

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K4J55323QF-GC Datasheet, PDF (9/49 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

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K4J55323QF-GC

256M GDDR3 SDRAM

INITIALIZATION

GDDR3 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than

those specified may result in undefined operation.

1. Apply power and keep CKE/RESET at low state ( All other inputs may be undefined)

- Apply VDD and VDDQ simultaneously

- Apply VDDQ before Vref. ( Inputs are not recognized as valid until after VREF is applied )

2. Required minimum 100us for the stable power before RESET pin transition to HIGH

- Upon power-up the address/command active termination value will automatically be set based off the state of RESET and CKE.

- On the rising edge of RESET the CKE pin is latched to determine the address and command bus termination value.

If CKE is sampled at a zero the address termination is set to 1/2 of ZQ.

If CKE is sampled at a one the address termination is set to ZQ.

- RESET must be maintained at a logic LOW level and CS at a logic high value during power-up to ensure that the DQ outputs will

be in a High-Z state, all active terminators off, and all DLLs off.

4. Minimum 200us delay required prior to applying any executable command after stable power and clock.

5. Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, then RESET and CKE should be

brought to HIGH,

6. Issue a PRECHARGE ALL command following after NOP command.

7. Issue a dummy MRS command ("00001000100001")

8. Issue a EMRS command (BA1BA0="01") to enable the DLL.

9. Issue MRS command (BA0BA1 = "00") to reset the DLL and to program the operating parameters.

20K clock cycles are required to lock the DLL.

9. Issue a PRECHARGE ALL command

10 . Issue at least two AUTO refresh command to update the driver impedance and calibrate the output drivers.

Following these requirements, the GDDR3 SDRAM is ready for normal operation.

VDDQ

VDD

VREF

RES

CKE

COMMAND

A0-A7, A9-A11

BA0, BA1

RDQS

WDQS

Ta0

Tb0

Tc0

Td0

Te0

Tf0

tATS

tATH

tCH

tCL

tIS

tIH

tIS

tIH

NOP

PRE

Dummy

MRS

EMRS

MRS

PRE

ACT

T=10ns

Power-up:

VDD and CK stable

T = 200us

High

tIS

tIH

tIS

tIH

CODE

ALL BANKS

tIS

tIH

tIS

tIH

ALL BANKS

CODE

tIS

tIH

tIS

tIH

tIS

tIH

tIS

tIH

BAO=L,

BA1 =L

BAO=H,

BA1 =L

BAO=L,

BA1 =L

Precharge

All Banks

tRP

tMRD

Load Mode Register

(Dummy MRS)

Load Extended

Mode Register

20K cycle

Load Mode Register

Precharge

DLL Reset

All Banks

tRP

tRFC

1st

Auto Refresh

2nd

Auto Refresh

-9-

Rev 1.8 (Apr. 2005)

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