K4J55323QF-GC Datasheet, PDF (15/49 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QF-GC
256M GDDR3 SDRAM
EXTENDED MODE REGISTER SET(EMRS)
The extended mode register stores the data output driver strength and on-die termination options. The
extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The GDDR3
SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode regis-
ter). The state of address pins A0 ~ A11 and BA0 in the same cycle as CS, RAS, CAS and WE going low are
written in the extended mode register. Six clock cycles are required to complete the write operation in the
extended mode register. 4 kinds of the output driver strength are supported by EMRS (A1, A0) code. The
mode register contents can be changed using the same command and clock cycle requirements during opera-
tion as long as all banks are in the idle state. "High" on BA0 is used for EMRS. Refer to the table for specific
codes.
BA1 BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
1
LP
ID
AL
tWR DLL
tWR
Termination Drive Strength
BA0 An ~ A0
0
MRS
1
EMRS
Vendor ID
A10 Vendor ID
0
Off
1
On
DLL
A6
0
1
DLL
Enable
Disable
Additive Latency
A9 A8
AL
00
0
01
1
1 0 Reserved
1 1 Reserved
Low Power
A11 Low Power
0
Disable
1
Enable
tWR
A7 A5 A4
000
001
010
011
100
101
110
111
tWR
3
4
5
6
7
Reserved
Reserved
Reserved
Drive Strength
A1 A0 Drive Strength
00
Autocal
01
30Ω
10
40Ω
11
50Ω
Termination
A3 A2 Termination
0 0 ODT Disabled
01
Reserved
10
ZQ/4
11
ZQ/2
* ZQ : Resistor connection pin for On-die termination
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Rev 1.8 (Apr. 2005)