K4J55323QF-GC Datasheet, PDF (28/49 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QF-GC
Random READ Accesses
T0
T1
T2
/CK
CK
COMMAND
READ
NOP
READ
ADDRESS
RDQS
Bank a,
Col n
CL = 8
Bank a,
Col b
DQ
256M GDDR3 SDRAM
T8
T8n
T9
T9n T10 T10n
NOP
NOP
NOP
DO
DO
DO
DO
DO
n
n
n
n
b
/CK
CK
COMMAND
ADDRESS
RDQS
T0
READ
Bank a,
Col n
DQ
T1
T7
NOP
READ
CL = 8
Bank a,
Col b
T8
T8n
T9
T9n T10 T10n
NOP
NOP
NOP
DO
DO
DO DO
n
n
n
n
DON’T CARE
TRANSITIONING DATA
NOTE :
1. DO n (or x or b or g) = data-out from column n (or column x or column x or column b or column g).
2. Burst length = 4
3. n’ or x or b’ or g’ indicates the next data-out following DO n or DO x or DO b OR DO g, respectively
4. READs are to an active row in any bank.
5. Shown with nominal t_AC and t_DQSQ.
6. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS.
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Rev 1.8 (Apr. 2005)