K4J55323QF-GC Datasheet, PDF (12/49 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QF-GC
256M GDDR3 SDRAM
CAS LATENCY (READ LATENCY)
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output
data. The latency can be set to 5~9 clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will
be available nominally coincident with clock edge n+m. Below table indicates the operating frequencies at which each CAS latency set-
ting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
SPEED
-12
-14
-16
-20
CL=9
≤ 800
≤ 700
-
-
CAS Latency
CL=8
-
-
≤ 600
-
Allowable operating
Frequency (MHz)
CL=7
CL=6
-
-
-
-
-
-
≤ 500
-
CL=5
-
-
-
-
T0
/CK
CK
COMMAND
READ
0
RDQS
DQ
T3
T4
NOP
CL = 5
NOP
T5
T5n
NOP
/CK
CK
COMMAND
RDQS
DQ
T0
READ
T4
T5
NOP
CL = 6
NOP
T6
T6n
NOP
Burst Length = 4 in the cases shown
Shown with nominal t_AC and nominal t_DSDQ
DON’T CARE
TRANSITIONING DATA
- 12 -
Rev 1.8 (Apr. 2005)