K4J55323QF-GC Datasheet, PDF (45/49 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QF-GC
256M GDDR3 SDRAM
CLOCK INPUT OPERATING CONDITIONS
Recommended operating conditions (0°C ≤ Tc ≤85°C ; VDD=2.0V + 0.1V, VDDQ=2.0V + 0.1V)
Parameter/ Condition
Symbol
Min
Clock Input Mid-Point Voltage ; CK and /CK
VMP(DC)
1.16
Clock Input Voltage Level; CK and /CK
VIN(DC)
0.42
Clock Input Differential Voltage ; CK and /CK
VID(DC)
0.22
Clock Input Differential Voltage ; CK and /CK
VID(AC)
0.22
Clock Input Crossing Point Voltage ; CK and /CK
VIX(AC)
VREF - 0.15
Max
1.36
VDDQ + 0.3
VDDQ + 0.5
VDDQ + 0.3
VREF + 0.15
Unit Note
V 1,2,3
V2
V 2,4
V4
V3
Note : 1. This provides a minimum of 1.16V to a maximum of 1.36V, and is always 70% of VDDQ
2. For AC operations, all DC clock requirements must be satisfied as well.
3. The value of VIX is expected to equal 70% VDDQ for the transmitting device and must track variations in the DC level of the same.
4. VID is the magnitude of the difference between the input level in CK and the input level on /CK.
5. The CK and /CK input reference level (for timing referenced to CK and /CK) is the point at which CK and /CK cross;
the input reference level for signals other than CK and /CK is VREF.
6. CK and /CK input slew rate must be > 3V/ns
V_REF
1.26V
GDDR3
240 Ω
ZQ
Z₀=60 Ω
V_DDQ
60Ω
10pf
Output Load Circuit
Note : 1 . Outputs measured into equivalent load of 10pf at a driver impedance of 40 Ω.
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Rev 1.8 (Apr. 2005)