K4J55323QF-GC Datasheet, PDF (21/49 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QF-GC
256M GDDR3 SDRAM
ON-DIE TERMINATION
Bus snooping for READ commands other than /CS is used to control the on-die termination. The GDDR3 SDRAM will dis-
able the on-die termination when a READ command is detected, regardless of the state of /CS. The on-die termination is
disabled x clocks after the READ command where x equals CL-1 and stay off for a duration of BL/2 + 2, as below figure,
Data Termination Disable Timing. In a two-rank system, both DRAM devices snoop the bus for READ commands to either
device and both will disable the on-die termination if a READ command is detected. The on-die termination for all other
pins on the device are always on for both a single-rank system and a dual-rank system.
The on-die termination value on address and control pins is determined during power-up in relation to the state of CKE on
the first transition of RESET. On the rising edge of RESET, if CKE is sampled LOW, then the configuration is determined to
be a single-rank system. The on-die termination is then set to one-half ZQ for the address pins. On the rising edge of
RESET, if CKE is sampled HIGH, then the configuration is determined to be a dual-rank system. The on-die termination for
the DQs, WDQS, and DM pins is set in the EMRS.
Data Termination Disable Timing
T0
T7
CK#
CK
COMMAND
READ
NOP
ADDRESS
RDQS
Bank a,
Col n
CL = 8
DQ
DQ
TERMINATION
T8
T8n
T9
T9n
T10
NOP
NOP
NOP
DO
n
GDDR3 Data Termination is Disabled
T11
NOP
DON’T CARE
Note : 1. DO n = data-out from column n.
2. Burst length = 4.
3. Three subsequent elements of data-out appear in the specified order following DO n.
4. Shown with nominal t_AC and t_DQSQ.
5. RDQS will start driving high one-half cycle prior to the first falling edge.
6. The Data Terminators are disabled starting at CL-1 and the duration is BL/2 + 2
7. READS to either rank disable both ranks’ termination regardless of the logic level of /CS.
TRANSITIONING DATA
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Rev 1.8 (Apr. 2005)