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K4J55323QF-GC Datasheet, PDF (47/49 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM
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K4J55323QF-GC
256M GDDR3 SDRAM
AC CHARACTERISTICS - I
Parameter
-14
Symbol
Min Max
-15
Min Max
-16
Min Max
-20
Unit
Min Max
DQS out access time from CK
tDQSCK -0.26 +0.26 -0.26 +0.26 -0.29 +0.29 -0.35 +0.35 ns
CK high-level width
tCH
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
CK low-level width
tCL
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
CK cycle time
CL=9
CL=8
1.4
3.3
1.4
3.3
-
-
-
-
ns
tCK
-
-
-
-
1.6
3.3
-
-
ns
CL=7
-
-
-
-
-
-
2.0
3.3 ns
WRITE Latency
tWL
5
-
5
-
5
-
4
-
tCK
DQ and DM input hold time relative to DQS
tDH
0.18
-
0.18
-
0.20
-
0.25
-
ns
DQ and DM input setup time relative to DQS
tDS
0.18
-
0.18
-
0.20
-
0.25
-
ns
Active termination setup time
tATS
10
-
10
-
10
-
10
-
ns
Active termination hold time
tATH
10
-
10
-
10
-
10
-
ns
DQS input high pulse width
tDQSH
0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK
DQS input low pulse widthl
tDQSL
0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK
Data strobe edge to Dout edge
tDQSQ
-
0.160
-
0.160
-
0.180
-
0.225 ns
DQS read preamble
tRPRE
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6 tCK
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6 tCK
Write command to first DQS latching transition
tDQSS WL-0.2 WL+0.2 WL-0.2 WL+0.2 WL-0.2 WL+0.2 WL-0.2 WL+0.2 tCK
DQS write preamble
tWPRE
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6 tCK
DQS write preamble setup time
tWPRES
0
-
0
-
0
-
0
-
ns
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6 tCK
Half strobe period
tCLmin
tCLmin
tCLmin
tCLmin
tHP
or
-
or
-
or
-
or
-
tCK
tCHmin
tCHmin
tCHmin
tCHmin
Data output hold time from DQS
tQH
tHP-0.16 - tHP-0.16 - tHP-0.18 -
tHP-
0.225
-
ns
Data-out high-impedance window from CK and /CK tHZ
-0.3
-
-0.3
-
-0.3
-
-0.3
-
ns
Data-out low-impedance window from CK and /CK tLZ
-0.3
-
-0.3
-
-0.3
-
-0.3
-
ns
Address and control input hold time
tIH
0.35
-
0.35
-
0.4
-
0.5
-
ns
Address and control input setup time
tIS
0.35
-
0.35
-
0.4
-
0.5
-
ns
Address and control input pulse width
tIPW
1.0
-
1.0
-
1.1
-
1.3
-
ns
Note
1
2
3
4
4
Note : 1. The WRITE latency can be set from 1 to 7 clocks. When the WRITE latency is set to 1 or 2 or 3 clocks(this case can be used regardless of fre
quency), the input buffers are turned on during the ACTIVE commands reducing the latency but added power. When the WRITE latency is set to
4 ~7 clocks , the input buffers are turned on during the WRITE commands for lower power operation. The WRITE latency which is over 4 clocks
can be used only in case that Write Latency*tCK is greater than 7ns.
2. A low to high transition on the WDQS line is not allowed in the half clock prior to the write preamble.
3. The last rising edge of WDQS after the write postamble must be riven high by the controller. WDQS can not be pulled high by
the on-die termination alone.
4. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific
voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ).
- 47 -
Rev 1.8 (Apr. 2005)
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