K4J55323QF-GC Datasheet, PDF (44/49 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QF-GC
256M GDDR3 SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Voltage on VDDQ supply relative to Vss
MAX Junction Temperature
Storage temperature
Power dissipation
Short Circuit Output Current
Symbol
VIN, VOUT
VDD
VDDQ
TJ
TSTG
PD
IOS
Value
Unit
-0.5 ~ VDDQ + 0.5V
V
-0.5 ~ 2.5
V
-0.5 ~ 2.5
V
+125
°C
-55 ~ +150
°C
TBD
W
50
mA
Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure periods may affect reliability.
POWER & DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to 0°C ≤ Tc ≤ 85°C ; VDD=2.0V + 0.1V, VDDQ=2.0V + 0.1V)
Parameter
Device Supply voltage
Output Supply voltage
Reference voltage
DC Input logic high voltage
DC Input logic low voltage
Output logic low voltage
AC Input logic high voltage
AC Input logic low voltage
Input leakage current
Any input 0V-<VIN -< VDDQ
(All other pins not under test = 0V)
Symbol
VDD
VDDQ
VREF
VIH (DC)
VIL (DC)
VOL(DC)
VIH(AC)
VIL(AC)
II
Min
1.9
1.9
0.69*VDDQ
VREF+0.15
-
-
VREF+0.25
-
-5
Typ
2.0
2.0
-
-
-
-
-
-
-
Max
2.1
2.1
0.71*VDDQ
-
VREF-0.15
0.76
-
VREF-0.25
Unit
V
V
V
V
V
V
V
V
5
uA
Note
1
1
3
4
4
4,5,6
4,5,6
Output leakage current
(DQs are disabled ; 0V-<VOUT -< VDDQ)
IIOZ
-5
-
5
uA
Note : 1.Under all conditions, VDDQ must be less than or equal to VDD.
3. VREF is expected to equal 70% of VDDQ for the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on
VREF may not exceed + 2 percent of the DC value. Thus, from 70% of VDDQ, VREF is allowed + 25mV for DC error and an additional +25mV
for AC noise.
4. The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to maintain
a valid level. The inputs require the AC value to be achieved during signal transition edge and the driver should achieve the same slew rate
through the AC values.
5. Input and output slew rate =3V/ns. If the input slew rate is less than 3V/ns, input timing may be compromised. All slew rate are measured between
Vih and Vil.
DQ and DM input slew rate must not deviate from DQS by more than 10%. If the DQ,DM and DQS slew rate is less than 3V/ns, timing is longer
than referenced to the mid-point but to the VIL(AC) maximum and VIH(AC) minimum points.
6. VIH overshoot : VIH(max) = VDDQ + 0.5V for a pulse width ≤ 500ps and the pulse width can not be greater than 1/3 of the cycle rate.
VIL undershoot : VIL(min)=0.0V for a pulse width ≤ 500ps and the pulse width can not be greater than 1/3 of the cycle rate.
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Rev 1.8 (Apr. 2005)