K4J55323QF-GC Datasheet, PDF (10/49 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QF-GC
256M GDDR3 SDRAM
MODE REGISTER SET(MRS)
The mode register stores the data for controlling the various operating modes of GDDR3 SDRAM. It programs CAS
latency, addressing mode, test mode and various vendor specific options to make GDDR3 SDRAM useful for variety of dif-
ferent applications. The default value of the mode register is not defined, therefore the mode register must be written after
EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE (The GDDR3
SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins
A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum six
clock cycles are requested to complete the write operation in the mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state.
The mode register is divided into various fields depending on functionality. The Burst length uses A0 ~ A2. CAS latency
(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is used for DLL reset. A9 ~ A11 are used
for Write latency. Refer to the table for specific codes for various addressing modes and CAS latencies.
BA1 BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
WL
DLL TM
CAS Latency
BT
Burst Length
BA0 An ~ A0
0
MRS
1
EMRS
0
Test Mode
A7 mode
0 Normal
1
Test
Burst Type
A3 Burst Type
0 Sequential
1 Reserved
Write Latency
A11 A10 A9
000
001
010
011
100
101
110
111
Write Latency
Reserved
1
2
3
4
5
6
Reserved
DLL
A8
0
1
DLL Reset
No
Yes
CAS Latency
A6 A5 A4
000
001
010
011
100
101
110
111
CAS Latency
8
9
Reserved
Reserved
Reserved
5
6
7
Burst Length
A2 A1 A0
000
001
010
011
100
101
110
111
Burst Length
Reserved
Reserved
4
Reserved
Reserved
Reserved
Reserved
Reserved
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Rev 1.8 (Apr. 2005)