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| K4B2G0446D Datasheet, PDF (61/64 Pages) Samsung semiconductor – 2Gb D-die DDR3L SDRAM | |||
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K4B2G0446D
K4B2G0846D
datasheet
Rev. 1.01
DDR3L SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
tIS
tIH
CK
CK
DQS
tIS tIH
DQS
VDDQ
tDS tDH
VIH(AC) min
VREF to ac
region
VIH(DC) min
VREF(DC)
VIL(DC) max
nominal slew
rate
VIL(AC) max
VSS
tVAC
tDS tDH
tVAC
nominal
slew rate
VREF to ac
region
â TF
Setup Slew Rate=
Falling Signal
VREF(DC) - VIL(AC)max
â TF
â TR
SeRtiuspinSgleSwignRaalte=
VIH(AC)min - VREF(DC)
â TR
Figure 25. Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock).
- 61 -
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