K4B2G0446D Datasheet, PDF(15/64 Page) Samsung semiconductor

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K4B2G0446D Datasheet, PDF (15/64 Pages) Samsung semiconductor – 2Gb D-die DDR3L SDRAM

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K4B2G0446D

K4B2G0846D

datasheet

8.3 AC & DC Logic Input Levels for Differential Signals

8.3.1 Differential signals definition

VIH.DIFF.AC.MIN

tDVAC

VIH.DIFF.MIN

Rev. 1.01

DDR3L SDRAM

0.0

VIL.DIFF.MAX

VIL.DIFF.AC.MAX

half cycle

tDVAC

time

Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC

8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)

[ Table 9 ] Differential AC & DC Input Levels

DDR3-800/1066/1333/1600

Symbol

Parameter

1.35V

1.5V

unit NOTE

min

max

min

max

VIHdiff

differential input high

+0.18

NOTE 3

+0.20

NOTE 3

VILdiff

differential input low

NOTE 3

-0.18

NOTE 3

-0.20

VIHdiff(AC) differential input high ac 2 x (VIH(AC) - VREF)

NOTE 3

2 x (VIH(AC) - VREF)

NOTE 3

VILdiff(AC) differential input low ac

NOTE 3

2 x (VIL(AC) - VREF)

NOTE 3

2 x (VIL(AC) - VREF) V

NOTE :

1. Used to define a differential signal slew-rate.

2. for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS use VIH/VIL(AC) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group,

then the reduced level applies also here.

3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended sig-

nals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undersheet Specification"

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