K4B2G0446D Datasheet, PDF (18/64 Pages) Samsung semiconductor – 2Gb D-die DDR3L SDRAM

K4B2G0446D
K4B2G0846D
datasheet
Rev. 1.01
DDR3L SDRAM
8.4 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input
signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage V_IX is measured from the actual
cross point of true and complement signal to the mid level between of V_DD and V_SS.
V_DD
CK, DQS
V_IX
V_IX
V_IX
V_DD/2
CK, DQS
V_SS
Figure 4. VIX Definition
[ Table 13 ] Cross point voltage for differential input signals (CK, DQS) : 1.35V
Symbol
Parameter
V_IX
Differential Input Cross Point Voltage relative to V_DD/2 for CK,CK
V_IX
Differential Input Cross Point Voltage relative to V_DD/2 for DQS,DQS
NOTE :
1. The relationbetween Vix Min/Max and VSEL/VSEH should satisfy following.
(VDD/2) + Vix(Min) - VSEL ≥ 25mV
VSEH - ((VDD/2) + Vix(Max)) ≥ 25mV
DDR3L-800/1066/1333/1600
Min
Max
-150
150
-150
150
Unit NOTE
mV
1
mV
[ Table 14 ] Cross point voltage for differential input signals (CK, DQS) : 1.5V
Symbol
Parameter
V_IX
Differential Input Cross Point Voltage relative to V_DD/2 for CK,CK
V_IX
Differential Input Cross Point Voltage relative to V_DD/2 for DQS,DQS
DDR3-800/1066/1333/1600
Min
Max
-150
150
-175
175
-150
150
Unit NOTE
mV
mV
1
mV
NOTE :
1. Extended range for V_IX is only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing V_SEL / V_SEH of at least V_DD/2
±250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns.
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