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K4B2G0446D Datasheet, PDF (49/64 Pages) Samsung semiconductor – 2Gb D-die DDR3L SDRAM
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K4B2G0446D
K4B2G0846D
datasheet
Rev. 1.01
DDR3L SDRAM
[ Table 49 ] Timing Parameters by Speed Bin (Cont.)
Speed
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Parameter
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Data Strobe Timing
DQS, DQS differential READ Preamble
tRPRE
0.9
Note 19
0.9
Note 19
0.9
Note 19
0.9
Note 19
DQS, DQS differential READ Postamble
tRPST
0.3
Note 11
0.3
Note 11
0.3
Note 11
0.3
Note 11
DQS, DQS differential output high time
tQSH
0.38
-
0.38
-
0.4
-
0.4
-
DQS, DQS differential output low time
tQSL
0.38
-
0.38
-
0.4
-
0.4
-
DQS, DQS differential WRITE Preamble
tWPRE
0.9
-
0.9
-
0.9
-
0.9
-
DQS, DQS differential WRITE Postamble
tWPST
0.3
-
0.3
-
0.3
-
0.3
-
DQS, DQS rising edge output access time from rising
CK, CK
tDQSCK
-400
400
-300
300
-255
255
-225
225
DQS, DQS low-impedance time (Referenced from RL-
1)
tLZ(DQS)
-800
400
-600
300
-500
250
-450
225
DQS, DQS high-impedance time (Referenced from
RL+BL/2)
tHZ(DQS)
-
400
-
300
-
250
-
225
DQS, DQS differential input low pulse width
tDQSL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
DQS, DQS differential input high pulse width
tDQSH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
DQS, DQS rising edge to CK, CK rising edge
tDQSS
-0.25
0.25
-0.25
0.25
-0.25
0.25
-0.27
0.27
DQS,DQS falling edge setup time to CK, CK rising edge tDSS
0.2
-
0.2
-
0.2
-
0.18
-
DQS,DQS falling edge hold time to CK, CK rising edge tDSH
0.2
-
0.2
-
0.2
-
0.18
-
Command and Address Timing
DLL locking time
tDLLK
512
-
512
-
512
-
512
-
internal READ Command to PRECHARGE Command
delay
tRTP
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
Delay from start of internal write transaction to internal
read command
tWTR
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
WRITE recovery time
tWR
15
-
15
-
15
-
15
-
Mode Register Set command cycle time
tMRD
4
-
4
-
4
-
4
-
Mode Register Set command update delay
tMOD
max
(12nCK,15ns)
-
max
(12nCK,15ns)
-
max
(12nCK,15ns)
-
max
(12nCK,15ns)
-
CAS# to CAS# command delay
tCCD
4
-
4
-
4
-
4
-
Auto precharge write recovery + precharge time
tDAL(min)
WR + roundup (tRP / tCK(AVG))
Multi-Purpose Register Recovery Time
tMPRR
1
-
1
-
1
-
1
-
ACTIVE to PRECHARGE command period
tRAS
See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin”
ACTIVE to ACTIVE command period for 1KB page size tRRD
max
(4nCK,10ns)
-
max
(4nCK,7.5ns)
-
max
(4nCK,6ns)
-
max
(4nCK,6ns)
-
ACTIVE to ACTIVE command period for 2KB page size tRRD
max
(4nCK,10ns)
-
max
(4nCK,10ns)
-
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
Four activate window for 1KB page size
tFAW
40
-
37.5
-
30
-
30
-
Four activate window for 2KB page size
tFAW
50
-
50
-
45
-
40
-
1.35V
Command and Address setup time to CK, CK refer-
tIS(base)
AC160
215
-
140
-
80
-
60
-
enced to VIH(AC) / VIL(AC) levels
1.5V
tIS(base)
AC175
200
-
125
-
65
-
45
-
1.35V
tIH(base)
Command and Address hold time from CK, CK refer-
DC90
285
-
210
-
150
-
130
-
enced to VIH(AC) / VIL(AC) levels
1.5V
tIH(base)
DC100
275
200
140
120
-
1.35V
Command and Address setup time to CK, CK refer-
tIS(base)
AC135
365
-
290
-
205
-
185
-
enced to VIH(AC) / VIL(AC) levels
1.5V
tIS(base)
AC150
350
-
275
-
190
-
170
-
Control & Address Input pulse width for each input
tIPW
900
-
780
-
620
-
560
-
Calibration Timing
Power-up and RESET calibration time
tZQinitI
512
-
512
-
512
-
512
-
Normal operation Full calibration time
tZQoper
256
-
256
-
256
-
256
-
Normal operation short calibration time
tZQCS
64
-
64
-
64
-
64
-
Units NOTE
tCK 13, 19, g
tCK 11, 13, b
tCK(avg) 13, g
tCK(avg) 13, g
tCK
tCK
ps
13,f
ps
13,14,f
ps 12,13,14
tCK
tCK
tCK(avg)
tCK(avg)
tCK(avg)
29, 31
30, 31
c
c, 32
c, 32
nCK
e
e,18
ns
e
nCK
nCK
nCK
nCK
22
ns
e
e
e
ns
e
ns
e
ps
b,16
ps
b,16
ps
b,16
ps
b,16
ps
b,16,27
ps
b,16,27
ps
28
nCK
nCK
nCK
23
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