K4B2G0446D Datasheet, PDF (20/64 Pages) Samsung semiconductor – 2Gb D-die DDR3L SDRAM

K4B2G0446D
K4B2G0846D
datasheet
Rev. 1.01
DDR3L SDRAM
9.3 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V_OL(AC) and V_OH(AC)
for single ended signals as shown in Table 18 and Figure 6.
[ Table 18 ] Single-ended output slew rate definition
Description
Single ended output slew rate for rising edge
Measured
From
To
V_OL(AC)
V_OH(AC)
Single ended output slew rate for falling edge
V_OH(AC)
V_OL(AC)
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
Defined by
V_OH(AC)-V_OL(AC)
Delta TRse
V_OH(AC)-V_OL(AC)
Delta TFse
[ Table 19 ] Single-ended output slew rate
Parameter
Symbol
Operation
Voltage
DDR3-800
Min Max
DDR3-1066
Min Max
DDR3-1333
Min Max
DDR3-1600
Min Max
Units
Single ended output slew rate
SRQse
1.35V
1.5V
1.75
5¹⁾
1.75
5¹⁾
1.75
5¹⁾
1.75
5¹⁾
V/ns
2.5
5
2.5
5
2.5
5
2.5
5
V/ns
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
se : Single-ended Signals
For Ron = RZQ/7 setting
NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ signals in
the same byte lane are static (i.e they stay at either high or low).
- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining
DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.
V_OH(AC)
V_TT
V_OL(AC)
delta TFse
delta TRse
Figure 6. Single-ended Output Slew Rate Definition
- 20 -