K4B2G0446D Datasheet, PDF (48/64 Pages) Samsung semiconductor – 2Gb D-die DDR3L SDRAM

K4B2G0446D
K4B2G0846D
datasheet
Rev. 1.01
DDR3L SDRAM
14. Timing Parameters by Speed Grade
[ Table 49 ] Timing Parameters by Speed Bin
Clock Timing
Speed
Parameter
Minimum Clock Cycle Time (DLL off mode)
Average Clock Period
Clock Period
Average high pulse width
Average low pulse width
Clock Period Jitter
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
Cycle to Cycle Period Jitter during DLL locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
Cumulative error across n = 13, 14 ... 49, 50 cycles
Absolute clock HIGH pulse width
Absolute clock Low pulse width
Data Timing
DQS,DQS to DQ skew, per group, per access
DQ output hold time from DQS, DQS
DQ low-impedance time from CK, CK
DQ high-impedance time from CK, CK
Data setup time to DQS, DQS referenced to
V_IH(AC)V_IL(AC) levels
Data hold time from DQS, DQS referenced to
V_IH(AC)V_IL(AC) levels
Data setup time to DQS, DQS referenced to
V_IH(AC)V_IL(AC) levels
DQ and DM Input pulse width for each input
Symbol
DDR3-800
MIN
MAX
DDR3-1066
MIN
MAX
DDR3-1333
MIN
MAX
DDR3-1600
MIN
MAX
Units NOTE
tCK(DLL_OF
F)
8
-
8
-
8
-
8
-
ns
6
tCK(avg)
See Speed Bins Table
ps
tCK(abs)
tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max +
tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max
ps
tCH(avg)
0.47
0.53
0.47
0.53
0.47
0.53
0.47
0.53 tCK(avg)
tCL(avg)
0.47
0.53
0.47
0.53
0.47
0.53
0.47
0.53 tCK(avg)
tJIT(per)
-100
100
-90
90
-80
80
-70
70
ps
tJIT(per, lck)
-90
90
-80
80
-70
70
-60
60
ps
tJIT(cc)
200
180
160
140
ps
tJIT(cc, lck)
180
160
140
120
ps
tERR(2per)
- 147
147
- 132
132
- 118
118
-103
103
ps
tERR(3per)
- 175
175
- 157
157
- 140
140
-122
122
ps
tERR(4per)
- 194
194
- 175
175
- 155
155
-136
136
ps
tERR(5per)
- 209
209
- 188
188
- 168
168
-147
147
ps
tERR(6per)
- 222
222
- 200
200
- 177
177
-155
155
ps
tERR(7per)
- 232
232
- 209
209
- 186
186
-163
163
ps
tERR(8per)
- 241
241
- 217
217
- 193
193
-169
169
ps
tERR(9per)
- 249
249
- 224
224
- 200
200
-175
175
ps
tERR(10per) - 257
257
- 231
231
- 205
205
-180
180
ps
tERR(11per) - 263
263
- 237
237
- 210
210
-184
184
ps
tERR(12per) - 269
269
- 242
242
- 215
215
-188
188
ps
tERR(nper)
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max
ps
24
tCH(abs)
0.43
-
0.43
-
0.43
-
0.43
-
tCK(avg) 25
tCL(abs)
0.43
-
0.43
-
0.43
-
0.43
-
tCK(avg) 26
tDQSQ
-
200
-
150
-
125
-
100
ps
13
tQH
0.38
-
0.38
-
0.38
-
0.38
-
tCK(avg) 13, g
tLZ(DQ)
-800
400
-600
300
-500
250
-450
225
ps
13,14, f
tHZ(DQ)
-
400
-
300
-
250
-
225
ps
13,14, f
1.35V
tDS(base)
AC160
90
-
40
-
-
-
-
-
ps
d, 17
1.5V
tDS(base)
AC175
75
-
25
-
-
-
-
-
ps
d, 17
1.35V
tDH(base)
DC90
160
-
110
-
75
-
55
-
ps
d, 17
1.5V
tDH(base)
DC100
150
-
100
-
65
-
45
-
ps
d, 17
1.35V
tDS(base)
AC135
140
-
90
-
45
-
25
-
ps
1.5V
tDS(base)
AC150
125
-
75
-
30
-
10
-
ps
tDIPW
600
-
490
-
400
-
360
-
ps
28
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