K4B2G0446D Datasheet, PDF (50/64 Pages) Samsung semiconductor – 2Gb D-die DDR3L SDRAM

K4B2G0446D
K4B2G0846D
datasheet
Rev. 1.01
DDR3L SDRAM
[ Table 49 ] Timing Parameters by Speed Bin (Cont.)
Speed
DDR3-800
Parameter
Symbol
MIN
MAX
Reset Timing
Exit Reset from CKE HIGH to a valid command
max(5nCK,
tXPR
tRFC +
-
10ns)
Self Refresh Timing
Exit Self Refresh to commands not requiring a locked
DLL
max(5nCK,t
tXS
RFC +
10ns)
-
Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK(min)
-
Minimum CKE low width for Self refresh entry to exit
timing
tCKESR
tCKE(min) +
1tCK
-
Valid Clock Requirement after Self Refresh Entry
(SRE) or Power-Down Entry (PDE)
tCKSRE
max(5nCK,
10ns)
-
Valid Clock Requirement before Self Refresh Exit
(SRX) or Power-Down Exit (PDX) or Reset Exit
tCKSRX
max(5nCK,
10ns)
-
Power Down Timing
Exit Power Down with DLL on to any valid com-
mand;Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
max
tXP
(3nCK,
-
7.5ns)
Exit Precharge Power Down with DLL frozen to com-
mands requiring a locked DLL
tXPDLL
max
(10nCK,
24ns)
-
CKE minimum pulse width
max
tCKE
(3nCK,
-
7.5ns)
Command pass disable delay
tCPDED
1
-
Power Down Entry to Exit Timing
tPD
tCKE(min) 9*tREFI
Timing of ACT command to Power Down entry
tACTPDEN
1
-
Timing of PRE command to Power Down entry
tPRPDEN
1
-
Timing of RD/RDA command to Power Down entry
tRDPDEN RL + 4 +1
-
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
WL + 4
tWRPDEN +(tWR/
-
tCK(avg))
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRAPDEN
WL + 4
+WR +1
-
Timing of WR command to Power Down entry
(BC4MRS)
WL + 2
tWRPDEN +(tWR/
-
tCK(avg))
Timing of WRA command to Power Down entry
(BC4MRS)
tWRAPDEN
WL +2 +WR
+1
-
Timing of REF command to Power Down entry
tREFPDEN
1
-
Timing of MRS command to Power Down entry
tMRSPDEN tMOD(min)
-
ODT Timing
ODT high time without write command or with write
command and BC4
ODTH4
4
-
ODT high time with Write command and BL8
ODTH8
6
-
Asynchronous RTT turn-on delay (Power-Down with
DLL frozen)
tAONPD
2
8.5
Asynchronous RTT turn-off delay (Power-Down with
DLL frozen)
tAOFPD
2
8.5
RTT turn-on
tAON
-400
400
RTT_NOM and RTT_WR turn-off time from ODTLoff
reference
tAOF
0.3
0.7
RTT dynamic change skew
tADC
0.3
0.7
Write Leveling Timing
First DQS pulse rising edge after tDQSS margining
mode is programmed
tWLMRD
40
-
DQS/DQS delay after tDQS margining mode is pro-
grammed
tWLDQSEN
25
-
Write leveling setup time from rising CK, CK crossing
to rising DQS, DQS crossing
tWLH
325
-
Write leveling hold time from rising DQS, DQS cross-
ing to rising CK, CK crossing
tWLH
325
-
Write leveling output delay
tWLO
0
9
Write leveling output error
tWLOE
0
2
DDR3-1066
MIN
MAX
max(5nCK,
tRFC +
-
10ns)
max(5nCK,t
RFC +
-
10ns)
tDLLK(min)
-
tCKE(min) +
1tCK
-
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
max
(3nCK,
7.5ns)
max
(10nCK,
24ns)
max
(3nCK,
5.625ns)
1
tCKE(min)
1
1
RL + 4 +1
WL + 4
+(tWR/
tCK(avg))
WL + 4
+WR +1
WL + 2
+(tWR/
tCK(avg))
WL +2 +WR
+1
1
tMOD(min)
-
-
-
-
9*tREFI
-
-
-
-
-
-
-
-
-
4
-
6
-
2
8.5
2
8.5
-300
300
0.3
0.7
0.3
0.7
40
-
25
-
245
-
245
-
0
9
0
2
DDR3-1333
MIN
MAX
DDR3-1600
MIN
MAX
max(5nCK,
max(5nCK,
tRFC +
-
tRFC +
-
10ns)
10ns)
max(5nCK,t
RFC +
10ns)
-
max(5nCK,t
RFC + 10ns)
-
tDLLK(min)
-
tDLLK(min)
-
tCKE(min) +
1tCK
-
tCKE(min) +
1tCK
-
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
max
(3nCK,6ns)
-
max
(3nCK,6ns)
-
max
(10nCK,
24ns)
max
(3nCK,
5.625ns)
1
tCKE(min)
1
1
RL + 4 +1
WL + 4
+(tWR/
tCK(avg))
WL + 4
+WR +1
WL + 2
+(tWR/
tCK(avg))
WL +2 +WR
+1
1
tMOD(min)
max
-
(10nCK,
24ns)
-
max
(3nCK,5ns)
-
1
9*tREFI tCKE(min)
-
1
-
1
-
RL + 4 +1
WL + 4
-
+(tWR/
tCK(avg))
-
WL + 4 +WR
+1
WL + 2
-
+(tWR/
tCK(avg))
-
WL +2 +WR
+1
-
1
-
tMOD(min)
-
-
-
9*tREFI
-
-
-
-
-
-
-
-
-
4
-
4
-
6
-
6
-
2
8.5
2
8.5
2
8.5
2
8.5
-250
250
-225
225
0.3
0.7
0.3
0.7
0.3
0.7
0.3
0.7
40
-
40
-
25
-
25
-
195
-
165
-
195
-
165
-
0
9
0
7.5
0
2
0
2
Units
nCK
nCK
tCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
ns
ns
ps
tCK(avg)
tCK(avg)
tCK
tCK
ps
ps
ns
ns
NOTE
2
15
20
20
9
10
9
10
20,21
7,f
8,f
f
3
3
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