K4B2G0446D Datasheet, PDF (53/64 Pages) Samsung semiconductor – 2Gb D-die DDR3L SDRAM

K4B2G0446D
K4B2G0846D
datasheet
Rev. 1.01
DDR3L SDRAM
14.3 Address/Command Setup, Hold and Derating :
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value (see
Table 50) to the ∆tIS and ∆tIH derating value (see Table 51) respectively.
Example: tIS (total setup time) = tIS(base) + ∆tIS Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
V_REF(DC) and the first crossing of V_IH(AC)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
V_REF(DC) and the first crossing of V_IL(AC)max. If the actual signal is always earlier than the nominal slew rate line between shaded ’V_REF(DC) to ac
region’, use nominal slew rate for derating value (see Figure 21). If the actual signal is later than the nominal slew rate line anywhere between shaded
’V_REF(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see Figure 23).
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V_IL(DC)max and the first crossing of V_REF(DC).
Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V_IH(DC)min and the first crossing of V_REF(DC). If
the actual signal is always later than the nominal slew rate line between shaded ’dc to V_REF(DC) region’, use nominal slew rate for derating value (see
Figure 22). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to V_REF(DC) region’, the slew rate of a tangent line
to the actual signal from the dc level to V_REF(DC) level is used for derating value (see Figure 24).
For a valid transition the input signal has to remain above/below V_IH/IL(AC) for some time tVAC (see Table 51).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached V_IH/IL(AC) at the time of the rising clock
transition) a valid input signal is still required to complete the transition and reach V_IH/IL(AC).
For slew rates in between the values listed in Table 51, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
[ Table 50 ] ADD/CMD Setup and Hold Base-Values for 1V/ns
[ps]
DDR3L-800
DDR3L-1066
DDR3L-1333
DDR3L-1600
reference
tIS(base) AC160
215
140
80
60
V_IH/L(AC)
tIS(base) AC135
365
290
205
185
V_IH/L(AC)
tIH(base)-DC90
285
210
150
130
V_IH/L(DC)
NOTE :
1. AC/DC referenced for 1V/ns Address/Command slew rate and 2 V/ns differential CK-Ck slew rate
2. The tIS(base) AC135 specifications are adjusted from the tIS(base) AC160 specification by adding an additional 125ps for DDR3L-800/1066 or 100ps for DDR3L-1333/1600
of derating to accommodate for the lower alternate threshold of 135mV and another 25ps to account for the earlier reference point [(160mV-135mV)/1 V/ns]
[ Table 51 ] Derating values DDR3-800/1066/1333/1600 tIS/tIH-AC/DC based
∆tIS, ∆tIH Derating [ps] AC/DC based
AC175 Threshold -> V_IH(AC) = V_REF(DC) + 175mV, V_IL(AC) = V_REF(DC) - 175mV
CLK,CLK Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH
2.0
88
50
88
50
88
50
96
58 104 66 112 74
1.5
59
34
59
34
59
34
67
42
75
50
83
58
1.0
0
0
0
0
0
0
8
CMD/
ADD ^0.9
-2
-4
-2
-4
-2
-4
6
8
16
16
24
24
4
14
12
22
20
Slew 0.8
-6
-10
-6
-10
-6
-10
2
-2
10
6
18
14
rate _0.7
-11
-16
-11
-16
-11
-16
-3
-8
5
V/ns
0
13
8
0.6 -17 -26 -17 -26 -17 -26
-9
-18
-1
-10
7
-2
0.5 -35 -40 -35 -40 -35 -40 -27 -32 -19 -24 -11 -16
0.4 -62 -60 -62 -60 -62 -60 -54 -52 -46 -44 -38 -36
1.2V/ns
∆tIS ∆tIH
120 84
91
68
32
34
30
30
26
24
21
18
15
8
-2
-6
-30 -26
1.0V/ns
∆tIS ∆tIH
128 100
99
84
40
50
38
46
34
40
29
34
23
24
5
10
-22 -10
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