K4X56163PE Datasheet, PDF (6/48 Pages) Samsung semiconductor – 16M x16 Mobile DDR SDRAM

K4X56163PE-L(F)G
Mobile-DDR SDRAM
Mode Register Definition
Mode Register Set(MRS)
The mode register is designed to support the various operating modes of DDR SDRAM. It includes CAS latency, addressing mode,
burst length, test mode and vendor specific options to make DDR SDRAM useful for variety of applications. The default value of the
mode register is not defined, therefore the mode register must be written in the power up sequence of DDR SDRAM. The mode reg-
ister is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with CKE already high prior to
writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going
low is written in the mode register. Two clock cycles are required to complete the write operation in the mode register. Even if the
power-up sequence is finished and some read or write operations is executed afterward, the mode register contents can be changed
with the same command and four clock cycles. This command must be issued only when all banks are in the idle state. If mode reg-
ister is changed, extended mode register automatically is reset and come into default state. So extended mode register must be set
again. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode
uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. BA0 and BA1 must be set to low
for normal DDR SDRAM operation.
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ^{Address Bus}
0
0
0
0
0
0
0
0
CAS Latency
BT
Burst Length
Mode Register
A6
A5
A4
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
CAS Latency
Reserve
Reserve
Reserve
3
Reserve
Reserve
Reserve
Reserve
A3 Burst Type
0
Sequential
1
Interleave
Burst Length
A2
A1
A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Burst type
Sequential
Interleave
Reserve
Reserve
2
2
4
4
8
8
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Figure.2 Mode Register Set
6
March 2004