K4X56163PE Datasheet, PDF (33/48 Pages) Samsung semiconductor – 16M x16 Mobile DDR SDRAM

K4X56163PE-L(F)G
Mobile-DDR SDRAM
AC Timming Parameters & Specifications
Parameter
Clock cycle time
Row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Active delay
Last data in to Read command
Col. address to Col. address delay
Clock high level width
Clock low level width
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS-in high level width
DQS-in low level width
DQS-in cycle time
Address and Control Input setup time
Address and Control Input hold time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
DQ & DM input pulse width
DQS write postamble time
Refresh interval time
Mode register set cycle time
Power down exit time
Auto refresh cycle time
Exit self refresh to active command
CL=3.0
CL=3.0
256Mb
Data hold from DQS to earliest DQ edge
Clock half period
Symbol
DDR200
Min
Max
tCK
10
tRC
80
tRAS
50
tRCD
30
tRP
30
tRRD
15
tWR
15
tDAL tWR+tRP
tCDLR
1
tCCD
1
tCH
0.45
0.55
tCL
0.45
0.55
tSAC
2.0
7.0
tDQSQ
0.7
tRPRE
0.9
1.1
tRPST
0.4
0.6
tDQSS
0.75
1.25
tWPRES
0
tWPREH 0.25
tDQSH
0.4
0.6
tDQSL
0.4
0.6
tDSC
0.9
1.1
tIS
1.5
tIH
1.5
tDS
1.1
tDH
1.1
tDIPW
2.2
tWPST
0.4
0.6
tREF
7.8
tMRD
2
tPDEX 1*tCK +tIS
tARFC
80
tSRFX
120
tQH
tHPmin -
1.0ns
tHP
tCLmin or
tCHmin
DDR133
Min
Max
15
90
60
30
30
15
30
tWR+tRP
1
1
0.45
0.55
0.45
0.55
2.0
7.0
0.9
0.9
1.1
0.4
0.6
0.75
1.25
0
0.25
0.4
0.6
0.4
0.6
0.9
1.1
2.0
2.0
1.5
1.5
3.0
0.4
0.6
7.8
2
1*tCK +tIS
80
120
tHPmin -
1.0ns
tCLmin or
tCHmin
Unit Note
ns
1
ns
ns
ns
ns
ns
ns
-
2
tCK
tCK
tCK
tCK
ns
3
ns
1
tCK
tCK
tCK
ns
4
tCK
tCK
tCK
tCK
ns
1
ns
1
ns
5,6
ns
5,6
ns
tCK
us
tCK
ns
ns
ns
ns
ns
33
March 2004