K4X56163PE Datasheet, PDF (11/48 Pages) Samsung semiconductor – 16M x16 Mobile DDR SDRAM

K4X56163PE-L(F)G
Mobile-DDR SDRAM
Row Active
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock(CK). The
DDR SDRAM has four independent banks, so two Bank Select addresses(BA0, BA1) are required. The Bank Activation command
must be applied before any Read or Write operation is executed. The delay from the Bank Activation command to the first read or
write command must meet or exceed the minimum of RAS to CAS delay time(tRCD min). Once a bank has been activated, it must be
precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between inter-
leaved Bank Activation commands(Bank A to Bank B and vice versa) is the Bank to Bank delay time(tRRD min).
Bank Activation Command Cycle
0
1
2
3
CK
CK
Bank A
Address _{Row Addr.}
Command
Bank A
Activate
RAS-CAS delay(tRCD)
NOP
NOP
NOP
4
5
Tn
Tn+1
Tn+2
Bank A
Col. Addr.
Write A
with Auto
Precharge
NOP
Bank B
Row Addr.
Bank A
Row. Addr.
RAS-RAS delay time(tRRD)
Bank B
Activate
NOP
Bank A
Activate
ROW Cycle Time(tRC)
: Don′t care
Figure.4 Bank activation command cycle timing
Read Bank
This command is used after the row activate command to initiate the burst read of data. The read command is initiated by activating
RAS, CS, CAS, and deasserting WE at the same clock sampling(rising) edge as described in the command truth table. The length of
the burst and the CAS latency time will be determined by the values programmed during the MRS cycle.
Write Bank
This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating
RAS, CS, CAS, and WE at the same clock sampling(rising) edge as described in the command truth table. The length of the burst will
be determined by the values programmed during the MRS cycle.
11
March 2004